{"id":"https://openalex.org/W4410492814","doi":"https://doi.org/10.1109/cicc63670.2025.10983468","title":"A 0.3-to-10.1 GHz 33.8f<sub>SRMS</sub>-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS","display_name":"A 0.3-to-10.1 GHz 33.8f<sub>SRMS</sub>-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS","publication_year":2025,"publication_date":"2025-04-13","ids":{"openalex":"https://openalex.org/W4410492814","doi":"https://doi.org/10.1109/cicc63670.2025.10983468"},"language":"en","primary_location":{"id":"doi:10.1109/cicc63670.2025.10983468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc63670.2025.10983468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100311200","display_name":"Hongzhi Wu","orcid":"https://orcid.org/0009-0003-3672-3462"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hongzhi Wu","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077093414","display_name":"Xuxu Cheng","orcid":"https://orcid.org/0000-0003-1717-0850"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xuxu Cheng","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101957692","display_name":"Liping Zhong","orcid":"https://orcid.org/0009-0008-3344-523X"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liping Zhong","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101795328","display_name":"Yangyi Zhang","orcid":"https://orcid.org/0009-0001-2606-7401"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yangyi Zhang","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100508325","display_name":"WU Weitao","orcid":"https://orcid.org/0009-0007-1445-9401"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Weitao Wu","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022925099","display_name":"Xiongshi Luo","orcid":"https://orcid.org/0000-0002-8960-1907"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiongshi Luo","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037098941","display_name":"Quan Pan","orcid":"https://orcid.org/0000-0001-8704-4505"},"institutions":[{"id":"https://openalex.org/I3045169105","display_name":"Southern University of Science and Technology","ror":"https://ror.org/049tv2d57","country_code":"CN","type":"education","lineage":["https://openalex.org/I3045169105"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Quan Pan","raw_affiliation_strings":["Southern University of Science and Technology,China"],"affiliations":[{"raw_affiliation_string":"Southern University of Science and Technology,China","institution_ids":["https://openalex.org/I3045169105"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5100311200"],"corresponding_institution_ids":["https://openalex.org/I3045169105"],"apc_list":null,"apc_paid":null,"fwci":0.7428,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.72090808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8712867498397827},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6765468120574951},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5884120464324951},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.568614661693573},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5415520668029785},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5364705920219421},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5164496898651123},{"id":"https://openalex.org/keywords/phase","display_name":"Phase (matter)","score":0.46192070841789246},{"id":"https://openalex.org/keywords/signal-generator","display_name":"Signal generator","score":0.4147319495677948},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3998379707336426},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.3767912983894348},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19368207454681396},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.19125112891197205},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1420971155166626},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.13140687346458435},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.08367156982421875}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8712867498397827},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6765468120574951},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5884120464324951},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.568614661693573},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5415520668029785},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5364705920219421},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5164496898651123},{"id":"https://openalex.org/C44280652","wikidata":"https://www.wikidata.org/wiki/Q104837","display_name":"Phase (matter)","level":2,"score":0.46192070841789246},{"id":"https://openalex.org/C207912722","wikidata":"https://www.wikidata.org/wiki/Q1259123","display_name":"Signal generator","level":3,"score":0.4147319495677948},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3998379707336426},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.3767912983894348},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19368207454681396},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.19125112891197205},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1420971155166626},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.13140687346458435},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.08367156982421875},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc63670.2025.10983468","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc63670.2025.10983468","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8199999928474426,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G2703551012","display_name":null,"funder_award_id":"2022YFB2803302,HC-CN-ZXIC20240528002","funder_id":"https://openalex.org/F4320335777","funder_display_name":"National Key Research and Development Program of China"}],"funders":[{"id":"https://openalex.org/F4320335777","display_name":"National Key Research and Development Program of China","ror":null}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2124415901","https://openalex.org/W2790961995","https://openalex.org/W3135290830","https://openalex.org/W4220990651","https://openalex.org/W4392745896","https://openalex.org/W6677121070","https://openalex.org/W6739431331","https://openalex.org/W6850601603"],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2301158783","https://openalex.org/W2369998856","https://openalex.org/W2133120878","https://openalex.org/W1969806930","https://openalex.org/W2369838978","https://openalex.org/W2108529481","https://openalex.org/W2360200482","https://openalex.org/W2002107209"],"abstract_inverted_index":{"The":[0],"growing":[1],"demand":[2],"for":[3,138,170,206],"higher":[4],"data":[5],"throughput":[6],"accelerates":[7],"the":[8,47,79,98,156,160,163,171,175,178,185,191,195,199],"development":[9],"of":[10,174,198],"high-speed":[11],"wireline":[12],"transceivers":[13],"with":[14,52,87,134,162],"improved":[15],"energy":[16],"efficiency":[17],"and":[18,49,72,107,144,190],"reduced":[19],"jitter":[20,44,74,106,143,196],"[1]\u2013[3].":[21],"A":[22],"wideband,":[23],"high-accuracy":[24],"multi-phase":[25,116,132],"clock":[26,157,201],"generator":[27,202],"(MPCG)":[28],"is":[29,93,119],"a":[30,39,68,82,88,103,114,126,168],"critical":[31],"component":[32],"in":[33,42,57,95,121],"this":[34,112,149],"development,":[35],"as":[36,55],"it":[37],"plays":[38],"significant":[40],"role":[41],"minimizing":[43],"on":[45,155],"both":[46,141],"transmitter":[48],"receiver":[50],"sides":[51],"low-power":[53],"consumption,":[54],"shown":[56],"Fig.":[58],"1.":[59],"In":[60],"recent":[61],"years,":[62],"MPCGs":[63],"have":[64],"evolved":[65],"to":[66,130],"achieve":[67],"wider":[69],"operating":[70,80,165,172],"range":[71,166,173],"lower":[73],"[4]\u2013[6].":[75],"To":[76,110],"further":[77,207],"extend":[78],"range,":[81],"two-phase":[83,99],"injection-locked-ring-oscillator-based":[84],"(IL-ROSC-based)":[85],"MPCG":[86],"quadrature-locked":[89],"loop":[90,128],"(QLL)":[91],"scheme":[92,101,118],"proposed":[94,120],"[7].":[96],"However,":[97],"injection":[100,117],"introduces":[102],"trade-off":[104],"between":[105,184],"phase":[108,136,146,152],"accuracy.":[109,147],"overcome":[111],"limitation,":[113],"two-step":[115],"[8].":[122],"This":[123],"approach":[124],"uses":[125],"delay-locked":[127],"(DLL)":[129],"generate":[131],"clocks":[133],"coarse":[135],"precision":[137],"injection,":[139],"maintaining":[140],"low":[142],"high":[145],"Yet,":[148],"method":[150],"imposes":[151],"accuracy":[153],"requirements":[154],"generated":[158],"by":[159,182],"DLL,":[161],"DLL's":[164],"becoming":[167],"bottleneck":[169],"MPCG.":[176],"Additionally,":[177],"frequency":[179],"deviation":[180],"caused":[181],"mismatches":[183],"voltage-controlled":[186],"delay":[187],"line":[188],"(VCDL)":[189],"ROSC":[192],"indicates":[193],"that":[194],"performance":[197],"multiphase":[200],"still":[203],"has":[204],"potential":[205],"improvement.":[208]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
