{"id":"https://openalex.org/W4410493045","doi":"https://doi.org/10.1109/cicc63670.2025.10983320","title":"On-Chip Circuit Harness Enabling Probe-Less, Position-Invariant and Massive Testing of Chiplets via Die Front/Back-Side Capacitive Coupling","display_name":"On-Chip Circuit Harness Enabling Probe-Less, Position-Invariant and Massive Testing of Chiplets via Die Front/Back-Side Capacitive Coupling","publication_year":2025,"publication_date":"2025-04-13","ids":{"openalex":"https://openalex.org/W4410493045","doi":"https://doi.org/10.1109/cicc63670.2025.10983320"},"language":"en","primary_location":{"id":"doi:10.1109/cicc63670.2025.10983320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc63670.2025.10983320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067430584","display_name":"Neelkamal Semwal","orcid":"https://orcid.org/0000-0002-8629-485X"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Neelkamal Semwal","raw_affiliation_strings":["National University of Singapore,Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027207316","display_name":"Luigi Fassio","orcid":"https://orcid.org/0000-0002-6080-4444"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Luigi Fassio","raw_affiliation_strings":["National University of Singapore,Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052037141","display_name":"Massimo Alioto","orcid":"https://orcid.org/0000-0002-4127-8258"},"institutions":[{"id":"https://openalex.org/I165932596","display_name":"National University of Singapore","ror":"https://ror.org/01tgyzw49","country_code":"SG","type":"education","lineage":["https://openalex.org/I165932596"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Massimo Alioto","raw_affiliation_strings":["National University of Singapore,Singapore"],"affiliations":[{"raw_affiliation_string":"National University of Singapore,Singapore","institution_ids":["https://openalex.org/I165932596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5067430584"],"corresponding_institution_ids":["https://openalex.org/I165932596"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11383032,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12039","display_name":"Electron and X-Ray Spectroscopy Techniques","score":0.9848999977111816,"subfield":{"id":"https://openalex.org/subfields/2508","display_name":"Surfaces, Coatings and Films"},"field":{"id":"https://openalex.org/fields/25","display_name":"Materials Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.717698872089386},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.7019511461257935},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5177021026611328},{"id":"https://openalex.org/keywords/capacitive-coupling","display_name":"Capacitive coupling","score":0.47859570384025574},{"id":"https://openalex.org/keywords/coupling","display_name":"Coupling (piping)","score":0.45814889669418335},{"id":"https://openalex.org/keywords/front-and-back-ends","display_name":"Front and back ends","score":0.4416991174221039},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.3658254146575928},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3619806170463562},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.35483992099761963},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3387429118156433},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25006842613220215},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.1900007426738739},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13371992111206055}],"concepts":[{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.717698872089386},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.7019511461257935},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5177021026611328},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.47859570384025574},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.45814889669418335},{"id":"https://openalex.org/C53016008","wikidata":"https://www.wikidata.org/wiki/Q620167","display_name":"Front and back ends","level":2,"score":0.4416991174221039},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.3658254146575928},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3619806170463562},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.35483992099761963},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3387429118156433},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25006842613220215},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.1900007426738739},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13371992111206055}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc63670.2025.10983320","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc63670.2025.10983320","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1594079841","https://openalex.org/W1996271793","https://openalex.org/W2071461165","https://openalex.org/W2080101991","https://openalex.org/W2112990568","https://openalex.org/W2141061687","https://openalex.org/W2145769900","https://openalex.org/W4214879625"],"related_works":["https://openalex.org/W4404521051","https://openalex.org/W2042913821","https://openalex.org/W2768092448","https://openalex.org/W2895758062","https://openalex.org/W2048683560","https://openalex.org/W2044770004","https://openalex.org/W1966070768","https://openalex.org/W1994341348","https://openalex.org/W2953512238","https://openalex.org/W4387574169"],"abstract_inverted_index":{"Modern":[0],"integrated":[1,40],"circuit":[2],"design":[3],"often":[4],"involves":[5],"integrating":[6],"multiple":[7],"smaller,":[8],"specialized":[9],"dies":[10],"(often":[11],"called":[12],"chiplets":[13,44,53,102],"or":[14,26],"tiles)":[15],"into":[16],"a":[17,61,90],"single":[18],"package.":[19],"This":[20,59],"approach,":[21],"known":[22],"as":[23],"chiplet-based":[24],"integration":[25,28,55],"3D":[27],"[1],":[29],"enables":[30],"the":[31,80,96],"creation":[32],"of":[33,77,98],"complex,":[34],"high-performance,":[35],"and":[36,56,71,101],"cost-effective":[37],"systems.":[38],"Heterogeneously":[39],"systems":[41,74],"based":[42],"on":[43],"invariably":[45],"require":[46],"an":[47],"extra":[48],"testing/screening":[49],"step":[50],"for":[51,79],"individual":[52],"before":[54],"full-system":[57],"testing.":[58],"creates":[60],"fundamental":[62],"challenge":[63],"in":[64],"ultra-low":[65],"power":[66],"<tex":[67],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[68],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$(\\sim\\mu":[69],"\\mathrm{W})$</tex>":[70],"low":[72],"cost":[73,110],"(few":[75],"tens":[76],"cents)":[78],"loT,":[81],"whose":[82],"total":[83],"testing":[84,99,109,113],"budget":[85],"is":[86,103],"generally":[87],"limited":[88],"to":[89,105],"few":[91],"cents.":[92],"Hence,":[93],"innovation":[94],"at":[95],"boundary":[97],"equipment":[100],"needed":[104],"significantly":[106],"reduce":[107],"chiplet":[108],"over":[111],"traditional":[112],"approaches.":[114]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}