{"id":"https://openalex.org/W4381732689","doi":"https://doi.org/10.1109/cicc57935.2023.10121246","title":"Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects","display_name":"Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4381732689","doi":"https://doi.org/10.1109/cicc57935.2023.10121246"},"language":"en","primary_location":{"id":"doi:10.1109/cicc57935.2023.10121246","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/cicc57935.2023.10121246","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045252697","display_name":"Harrison Liew","orcid":"https://orcid.org/0000-0003-3600-3951"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"Harrison Liew","raw_affiliation_strings":["Intel Corporation","U. C. Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]},{"raw_affiliation_string":"U. C. Berkeley","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088477949","display_name":"Farhana Sheikh","orcid":"https://orcid.org/0000-0001-5078-0816"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Farhana Sheikh","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003017713","display_name":"David Kehlet","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Kehlet","raw_affiliation_strings":["Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041784384","display_name":"Borivoje Nikoli\u0107","orcid":"https://orcid.org/0000-0003-2324-1715"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Borivoje Nikoli\u0107","raw_affiliation_strings":["U. C. Berkeley"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"U. C. Berkeley","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1227,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.41347115,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.8757616281509399},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7718653678894043},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5352628231048584},{"id":"https://openalex.org/keywords/bridge","display_name":"Bridge (graph theory)","score":0.53334641456604},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.524628221988678},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5038685202598572},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3643121123313904},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3319839835166931},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13961046934127808},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12999388575553894}],"concepts":[{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.8757616281509399},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7718653678894043},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5352628231048584},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.53334641456604},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.524628221988678},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5038685202598572},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3643121123313904},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3319839835166931},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13961046934127808},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12999388575553894},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C126322002","wikidata":"https://www.wikidata.org/wiki/Q11180","display_name":"Internal medicine","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc57935.2023.10121246","is_oa":false,"landing_page_url":"http://dx.doi.org/10.1109/cicc57935.2023.10121246","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W2524669578","https://openalex.org/W2539164722","https://openalex.org/W2587180584","https://openalex.org/W3005962614","https://openalex.org/W3083958169","https://openalex.org/W3187148842","https://openalex.org/W3217372878","https://openalex.org/W4200378000","https://openalex.org/W4206578696","https://openalex.org/W4220769636","https://openalex.org/W4225740429","https://openalex.org/W4280491905","https://openalex.org/W4285103121","https://openalex.org/W4285103215","https://openalex.org/W4296209134","https://openalex.org/W4308340461","https://openalex.org/W6728806124"],"related_works":["https://openalex.org/W2042913821","https://openalex.org/W2738154096","https://openalex.org/W2372289614","https://openalex.org/W2629813803","https://openalex.org/W2041067810","https://openalex.org/W2250518232","https://openalex.org/W3199170188","https://openalex.org/W2360137025","https://openalex.org/W2109445684","https://openalex.org/W2081082331"],"abstract_inverted_index":{"As":[0],"CMOS":[1],"scaling":[2],"has":[3,8,37,65],"slowed":[4],"down,":[5],"high-performance":[6],"computing":[7],"turned":[9],"to":[10,16,29],"2.5D":[11],"and":[12,20],"3D":[13],"heterogeneous":[14],"integration":[15],"simultaneously":[17],"increase":[18],"density":[19],"performance.":[21],"Vertical":[22],"die-to-die":[23],"(D2D)":[24],"interconnect":[25,56],"standards":[26,57],"are":[27],"required":[28],"enable":[30],"an":[31],"ecosystem":[32],"of":[33],"3D-stackable":[34],"chiplets,":[35],"as":[36],"been":[38],"proposed":[39],"in":[40],"a":[41,60],"draft":[42],"AIB-3D":[43],"specification":[44],"[1].":[45],"In":[46],"this":[47],"paper,":[48],"we":[49],"make":[50],"the":[51],"case":[52],"that":[53],"vertical":[54],"D2D":[55],"must":[58],"bridge":[59],"design":[61],"space":[62],"wider":[63],"than":[64],"existed":[66],"for":[67],"horizontal":[68],"interconnect,":[69],"with":[70],"wide-ranging":[71],"implications":[72],"on":[73],"architectural":[74],"specifications.":[75]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
