{"id":"https://openalex.org/W4376131456","doi":"https://doi.org/10.1109/cicc57935.2023.10121240","title":"Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits","display_name":"Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits","publication_year":2023,"publication_date":"2023-04-01","ids":{"openalex":"https://openalex.org/W4376131456","doi":"https://doi.org/10.1109/cicc57935.2023.10121240"},"language":"en","primary_location":{"id":"doi:10.1109/cicc57935.2023.10121240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc57935.2023.10121240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044592906","display_name":"Archisman Ghosh","orcid":"https://orcid.org/0000-0002-7842-030X"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Archisman Ghosh","raw_affiliation_strings":["Purdue University, IN,USA","Purdue University, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100674578","display_name":"Md. Abdur Rahman","orcid":"https://orcid.org/0000-0002-8684-8154"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Md. Abdur Rahman","raw_affiliation_strings":["Purdue University, IN,USA","Purdue University, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016409294","display_name":"Debayan Das","orcid":"https://orcid.org/0000-0003-1843-0124"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debayan Das","raw_affiliation_strings":["Purdue University, IN,USA","Intel Corp., Portland, OR, USA","Purdue University, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Intel Corp., Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Purdue University, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078467758","display_name":"Santosh Ghosh","orcid":"https://orcid.org/0000-0003-0069-7971"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Santosh Ghosh","raw_affiliation_strings":["Intel Corp.,Portland,OR,USA","Intel Corp., Portland, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corp.,Portland,OR,USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Portland, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056832262","display_name":"Shreyas Sen","orcid":"https://orcid.org/0000-0001-5566-8946"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shreyas Sen","raw_affiliation_strings":["Purdue University, IN,USA","Purdue University, IN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Purdue University, IN,USA","institution_ids":["https://openalex.org/I219193219"]},{"raw_affiliation_string":"Purdue University, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9722999930381775,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6426072716712952},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49021631479263306},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4648996889591217},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.45136192440986633},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4356152415275574},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4329123795032501},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.41597670316696167},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3259233236312866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2819598317146301},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.2603764533996582}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6426072716712952},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49021631479263306},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4648996889591217},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.45136192440986633},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4356152415275574},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4329123795032501},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.41597670316696167},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3259233236312866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2819598317146301},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.2603764533996582}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc57935.2023.10121240","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc57935.2023.10121240","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6700000166893005,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W4386968318","https://openalex.org/W2052455055","https://openalex.org/W2090237663","https://openalex.org/W2158864330","https://openalex.org/W2224788396","https://openalex.org/W2495024767","https://openalex.org/W1989324326","https://openalex.org/W2308963021","https://openalex.org/W1487986186","https://openalex.org/W4200240321"],"abstract_inverted_index":{"Side":[0],"channel":[1],"analysis":[2],"(SCA)":[3],"is":[4,161],"a":[5,14,47,189],"low":[6,71],"time-complexity":[7],"technique":[8,198],"of":[9,90,129,144,183,213],"extracting":[10],"secret":[11],"information":[12],"from":[13],"cryptographic":[15,79],"1C,":[16],"which":[17,206],"calls":[18],"for":[19,158,167,175,199,218],"low-overhead":[20,197],"generic":[21,34],"resilience":[22],"techniques.":[23],"While":[24],"architectural":[25],"and":[26,61,73,87,136,147,193,203],"logical":[27],"countermeasures":[28,36,94,217],"[1]":[29],"are":[30],"explored":[31],"widely,":[32],"recently":[33],"circuit-level":[35,130],"(e.g.":[37],"voltage":[38],"regulators":[39],"[2]":[40],"\u2013[4],":[41],"power":[42,99,202],"balancing":[43],"[5]":[44],"or":[45],"through":[46],"switched":[48],"capacitor":[49],"current":[50],"equalizer":[51],"[6],":[52],"using":[53],"an":[54,195],"on-chip":[55],"machine":[56],"learning":[57],"model":[58],"[7],":[59],"[8],":[60],"signature":[62],"attenuation":[63],"[9],":[64],"[10])":[65],"have":[66,95,120],"gained":[67],"prominence":[68],"due":[69],"to":[70,101,110,162],"overheads":[72],"being":[74],"architecture":[75],"agnostic.":[76],"Typical":[77],"digital":[78,145,185],"core":[80],"has":[81],"two":[82],"controllable":[83],"ports,":[84],"i.e.,":[85],"supply":[86,215],"clock.":[88],"Most":[89],"the":[91,98,103,111,127,133,159,176,180,214],"circuitlevel/physical":[92],"layer":[93],"primarily":[96],"utilized":[97],"port":[100,216],"reduce":[102],"side-channel":[104],"leakage":[105,152],"signal-to-noise":[106],"ratio":[107],"(SNR).":[108],"Related":[109],"clocking":[112,134],"port,":[113],"well-studied":[114],"system-level":[115],"clock":[116,192],"frequency":[117],"randomization":[118],"techniques":[119],"been":[121],"deemed":[122],"ineffective":[123],"with":[124,141,211],"post-processing.":[125],"However,":[126],"impact":[128,149],"changes":[131],"in":[132],"circuitry":[135],"its":[137,148],"device-circuit-system":[138],"level":[139],"interactions":[140],"inherent":[142,181],"propeities":[143],"circuits":[146,186],"on":[150,221],"SCA":[151,222],"remains":[153],"unexplored.":[154],"Another":[155],"key":[156],"requirement":[157],"countermeasure":[160],"make":[163],"it":[164],"fully":[165],"synthesizable":[166],"scalability":[168],"across":[169],"different":[170],"technology":[171],"nodes.":[172],"This":[173],"work,":[174],"first":[177],"time,":[178],"exploits":[179],"variability":[182],"CMOS":[184],"by":[187],"providing":[188],"controlled":[190],"slewed":[191],"demonstrates":[194],"extremely":[196],"immunity":[200],"against":[201],"EM":[204],"SCA,":[205],"can":[207],"be":[208],"easily":[209],"combined":[210],"any":[212],"multiplicative":[219],"effect":[220],"resilience.":[223]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3}],"updated_date":"2026-07-25T09:21:30.201066","created_date":"2025-10-10T00:00:00"}
