{"id":"https://openalex.org/W3017745964","doi":"https://doi.org/10.1109/cicc48029.2020.9075913","title":"HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis","display_name":"HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3017745964","doi":"https://doi.org/10.1109/cicc48029.2020.9075913","mag":"3017745964"},"language":"en","primary_location":{"id":"doi:10.1109/cicc48029.2020.9075913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc48029.2020.9075913","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5086890914","display_name":"Paolo Mantovani","orcid":"https://orcid.org/0000-0002-1901-8732"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paolo Mantovani","raw_affiliation_strings":["Columbia University, New York, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052253321","display_name":"Robert Margelli","orcid":null},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Robert Margelli","raw_affiliation_strings":["Columbia University, New York, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027759717","display_name":"Davide Giri","orcid":"https://orcid.org/0000-0003-4101-4516"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Davide Giri","raw_affiliation_strings":["Columbia University, New York, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009992367","display_name":"Luca P. Carloni","orcid":"https://orcid.org/0000-0001-5600-8931"},"institutions":[{"id":"https://openalex.org/I78577930","display_name":"Columbia University","ror":"https://ror.org/00hj8s172","country_code":"US","type":"education","lineage":["https://openalex.org/I78577930"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Luca P. Carloni","raw_affiliation_strings":["Columbia University, New York, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Columbia University, New York, NY","institution_ids":["https://openalex.org/I78577930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.8883,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.85350049,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"8"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7097237706184387},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.7086054086685181},{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.6909125447273254},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6552242040634155},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6419976949691772},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5774332284927368},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5524230003356934},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5018858909606934},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4845923185348511},{"id":"https://openalex.org/keywords/reusability","display_name":"Reusability","score":0.48184096813201904},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.48164287209510803},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.467263400554657},{"id":"https://openalex.org/keywords/32-bit","display_name":"32-bit","score":0.43347200751304626},{"id":"https://openalex.org/keywords/processor-design","display_name":"Processor design","score":0.4123850166797638},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4015761911869049},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.3487166166305542},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26502472162246704},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.23181796073913574},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17289605736732483}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7097237706184387},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.7086054086685181},{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.6909125447273254},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6552242040634155},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6419976949691772},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5774332284927368},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5524230003356934},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5018858909606934},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4845923185348511},{"id":"https://openalex.org/C137981799","wikidata":"https://www.wikidata.org/wiki/Q1369184","display_name":"Reusability","level":3,"score":0.48184096813201904},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.48164287209510803},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.467263400554657},{"id":"https://openalex.org/C75695347","wikidata":"https://www.wikidata.org/wiki/Q225147","display_name":"32-bit","level":2,"score":0.43347200751304626},{"id":"https://openalex.org/C526435321","wikidata":"https://www.wikidata.org/wiki/Q1303814","display_name":"Processor design","level":2,"score":0.4123850166797638},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4015761911869049},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.3487166166305542},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26502472162246704},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.23181796073913574},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17289605736732483},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc48029.2020.9075913","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc48029.2020.9075913","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6299999952316284,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":43,"referenced_works":["https://openalex.org/W1612189975","https://openalex.org/W1919071401","https://openalex.org/W1926668751","https://openalex.org/W1971487398","https://openalex.org/W1974274517","https://openalex.org/W1977813547","https://openalex.org/W1983394510","https://openalex.org/W1988994727","https://openalex.org/W1999085092","https://openalex.org/W2016310205","https://openalex.org/W2038509324","https://openalex.org/W2048081424","https://openalex.org/W2090540916","https://openalex.org/W2094998159","https://openalex.org/W2100720925","https://openalex.org/W2118578839","https://openalex.org/W2141280299","https://openalex.org/W2150347868","https://openalex.org/W2151799560","https://openalex.org/W2160566592","https://openalex.org/W2161038820","https://openalex.org/W2277529441","https://openalex.org/W2293771166","https://openalex.org/W2321294477","https://openalex.org/W2331352034","https://openalex.org/W2397193845","https://openalex.org/W2476162426","https://openalex.org/W2481725867","https://openalex.org/W2522116871","https://openalex.org/W2587318777","https://openalex.org/W2623461819","https://openalex.org/W2803384426","https://openalex.org/W3145012771","https://openalex.org/W3147194359","https://openalex.org/W3148896160","https://openalex.org/W3209032895","https://openalex.org/W4233718422","https://openalex.org/W4240110784","https://openalex.org/W4244878519","https://openalex.org/W6647673961","https://openalex.org/W6649797076","https://openalex.org/W6727245067","https://openalex.org/W6987020231"],"related_works":["https://openalex.org/W2102117846","https://openalex.org/W2028583644","https://openalex.org/W2533063779","https://openalex.org/W2035070505","https://openalex.org/W2119501389","https://openalex.org/W2000188956","https://openalex.org/W182515070","https://openalex.org/W4243704847","https://openalex.org/W2139653418","https://openalex.org/W3017745964"],"abstract_inverted_index":{"The":[0],"growing":[1],"complexity":[2],"of":[3,8,17,38,49,82,112],"system-on-chip":[4],"fuels":[5],"the":[6,14,34,47,61,80,108],"adoption":[7],"high-level":[9],"synthesis":[10,97],"(HLS)":[11],"to":[12,115],"reduce":[13],"design":[15,48],"time":[16],"application-specific":[18],"accelerators.":[19],"General-purpose":[20],"processors,":[21],"however,":[22],"are":[23,33],"still":[24],"designed":[25,66],"using":[26],"RTL":[27,96],"and":[28,55,69,110],"logic":[29],"synthesis.":[30],"Yet":[31],"they":[32],"most":[35,39],"complex":[36],"components":[37],"systems-on-chip.":[40],"We":[41,57,76],"show":[42],"that":[43,89],"HLS":[44,74,114,128],"can":[45],"simplify":[46],"processors":[50],"while":[51],"enhancing":[52],"their":[53],"customization":[54],"reusability.":[56],"present":[58],"HL5":[59,78],"as":[60],"first":[62],"32-bit":[63],"RISC-V":[64],"microprocessor":[65],"with":[67,71,93],"SystemC":[68],"optimized":[70],"a":[72,94,100,124],"commercial":[73,101],"tool.":[75],"evalute":[77],"through":[79],"execution":[81],"software":[83],"programs":[84],"on":[85],"an":[86],"experimental":[87],"infrastructure":[88],"combines":[90],"FPGA":[91],"emulation":[92],"standard":[95],"flow":[98],"for":[99],"32":[102],"nm":[103],"CMOS":[104],"technology.":[105],"By":[106],"describing":[107],"challenges":[109],"opportunities":[111],"applying":[113],"processor":[116],"design,":[117],"our":[118],"paper":[119],"aims":[120],"also":[121],"at":[122],"sparking":[123],"renewed":[125],"interest":[126],"in":[127],"research.":[129]},"counts_by_year":[{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
