{"id":"https://openalex.org/W3017968097","doi":"https://doi.org/10.1109/cicc48029.2020.9075883","title":"A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC","display_name":"A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC","publication_year":2020,"publication_date":"2020-03-01","ids":{"openalex":"https://openalex.org/W3017968097","doi":"https://doi.org/10.1109/cicc48029.2020.9075883","mag":"3017968097"},"language":"en","primary_location":{"id":"doi:10.1109/cicc48029.2020.9075883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc48029.2020.9075883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5003541204","display_name":"Chengshuo Yu","orcid":"https://orcid.org/0000-0003-0897-7871"},"institutions":[{"id":"https://openalex.org/I115228651","display_name":"Agency for Science, Technology and Research","ror":"https://ror.org/036wvzt09","country_code":"SG","type":"government","lineage":["https://openalex.org/I115228651"]},{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Chengshuo Yu","raw_affiliation_strings":["Institute of Microelectronics, A* STAR, Singapore"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, A* STAR, Singapore","institution_ids":["https://openalex.org/I4210090209","https://openalex.org/I115228651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056917810","display_name":"Taegeun Yoo","orcid":"https://orcid.org/0000-0001-9876-7725"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Taegeun Yoo","raw_affiliation_strings":["1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076628109","display_name":"Tony Tae-Hyoung Kim","orcid":"https://orcid.org/0000-0002-1779-1799"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Tony Tae-Hyoung Kim","raw_affiliation_strings":["1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069583051","display_name":"Kevin Chai Tshun Chuan","orcid":null},"institutions":[{"id":"https://openalex.org/I115228651","display_name":"Agency for Science, Technology and Research","ror":"https://ror.org/036wvzt09","country_code":"SG","type":"government","lineage":["https://openalex.org/I115228651"]},{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Kevin Chai Tshun Chuan","raw_affiliation_strings":["Institute of Microelectronics, A* STAR, Singapore"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, A* STAR, Singapore","institution_ids":["https://openalex.org/I4210090209","https://openalex.org/I115228651"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035469250","display_name":"Bongjin Kim","orcid":"https://orcid.org/0000-0001-5397-9628"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bongjin Kim","raw_affiliation_strings":["1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"1School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5003541204"],"corresponding_institution_ids":["https://openalex.org/I115228651","https://openalex.org/I4210090209"],"apc_list":null,"apc_paid":null,"fwci":7.9882,"has_fulltext":false,"cited_by_count":98,"citation_normalized_percentile":{"value":0.98153485,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":96,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.872433602809906},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5322553515434265},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5201854705810547},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5103468298912048},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4878509044647217},{"id":"https://openalex.org/keywords/column","display_name":"Column (typography)","score":0.4711008667945862},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.45800328254699707},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.45403218269348145},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.4455816149711609},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.4451165795326233},{"id":"https://openalex.org/keywords/dot-product","display_name":"Dot product","score":0.435162752866745},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.42345988750457764},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3420066833496094},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.30864936113357544},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.21694794297218323},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21390300989151},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.13555043935775757},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.13510164618492126},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12751632928848267},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11992713809013367}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.872433602809906},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5322553515434265},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5201854705810547},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5103468298912048},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4878509044647217},{"id":"https://openalex.org/C2780551164","wikidata":"https://www.wikidata.org/wiki/Q2306599","display_name":"Column (typography)","level":3,"score":0.4711008667945862},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.45800328254699707},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.45403218269348145},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.4455816149711609},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.4451165795326233},{"id":"https://openalex.org/C32900221","wikidata":"https://www.wikidata.org/wiki/Q181365","display_name":"Dot product","level":2,"score":0.435162752866745},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.42345988750457764},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3420066833496094},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.30864936113357544},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.21694794297218323},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21390300989151},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.13555043935775757},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.13510164618492126},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12751632928848267},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11992713809013367},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc48029.2020.9075883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc48029.2020.9075883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2020 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1999085092","https://openalex.org/W2527492855","https://openalex.org/W2792893539","https://openalex.org/W2898665561","https://openalex.org/W2898913080","https://openalex.org/W3015887053","https://openalex.org/W6649797076","https://openalex.org/W6727867346"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2119312496","https://openalex.org/W2085719533","https://openalex.org/W2373152541","https://openalex.org/W4247460323","https://openalex.org/W2537086382","https://openalex.org/W2174410816","https://openalex.org/W2107909712"],"abstract_inverted_index":{"A":[0,31,166],"novel":[1],"8T":[2,33],"SRAM":[3,26,34,71,102,175],"-based":[4],"bitcell":[5,15,35,176],"is":[6,37,168,191],"proposed":[7,14,70],"for":[8,39,78,82,87,101,126,129],"current-based":[9],"compute-in-memory":[10,72],"dot-product":[11,110],"operations.":[12],"The":[13,89,104,145,184],"with":[16,47,163],"two":[17],"extra":[18],"NMOS":[19],"transistors":[20],"(vs.":[21],"standard":[22],"6T":[23],"SRAM)":[24],"decouples":[25],"read":[27],"and":[28,60,84,134,142,172,201],"write":[29],"operation.":[30],"128\u00d7128":[32],"array":[36,177],"built":[38],"processing":[40],"a":[41,98,161],"vector-matrix":[42],"multiplication":[43],"(or":[44],"parallel":[45],"dot-products)":[46],"64x":[48,76],"binary":[49,55],"(0":[50],"or":[51,57],"1)":[52],"inputs,":[53],"64\u00d7128":[54],"(-1":[56],"+1)":[58],"weights,":[59],"128x":[61],"1-5bit":[62,194],"outputs.":[63],"Each":[64],"column":[65],"(i.e.":[66,157],"neuron)":[67],"of":[68,75,155,187],"the":[69,93,108,151,173,188],"macro":[73],"consists":[74],"bitcells":[77,81,86,125],"dot-product,":[79],"32x":[80,85],"ADC,":[83],"calibration.":[88],"column-based":[90],"neuron":[91],"minimizes":[92],"ADC":[94,106,195],"overhead":[95],"by":[96,119],"reusing":[97],"sense":[99],"amplifier":[100],"read.":[103],"column-wise":[105],"converts":[107],"analog":[109],"results":[111,137,149],"to":[112,117],"N-bit":[113],"output":[114],"codes":[115],"(N=1":[116],"5)":[118],"sweeping":[120],"reference":[121],"levels":[122],"using":[123,170,197],"replica":[124],"2N-1":[127],"cycles":[128],"each":[130],"conversion.":[131],"Monte-Carlo":[132],"simulations":[133],"test-chip":[135,167],"measurement":[136],"have":[138],"verified":[139],"both":[140],"linearity":[141],"process":[143],"variation.":[144],"largest":[146],"variation":[147],"(\u03c3=2.48%)":[148],"in":[150],"MNIST":[152],"classification":[153],"accuracy":[154],"96.2%":[156],"0.4%":[158],"lower":[159],"than":[160],"baseline":[162],"no":[164],"variation).":[165],"fabricated":[169],"65nm,":[171],"16K":[174],"occupies":[178],"0.055mm":[179],"<sup":[180],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[181],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[182],".":[183],"energy":[185],"efficiency":[186],"1bit":[189],"operation":[190],"490-to-15.8TOPS/W":[192],"at":[193],"mode":[196],"0.45/0.8V":[198],"core":[199],"supply":[200],"200MHz.":[202]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":8},{"year":2024,"cited_by_count":12},{"year":2023,"cited_by_count":26},{"year":2022,"cited_by_count":25},{"year":2021,"cited_by_count":21},{"year":2020,"cited_by_count":5}],"updated_date":"2026-03-27T14:29:43.386196","created_date":"2025-10-10T00:00:00"}