{"id":"https://openalex.org/W2964620109","doi":"https://doi.org/10.1109/cicc.2019.8780267","title":"Nanoscale CMOS Implications on Analog/Mixed-Signal Design","display_name":"Nanoscale CMOS Implications on Analog/Mixed-Signal Design","publication_year":2019,"publication_date":"2019-04-01","ids":{"openalex":"https://openalex.org/W2964620109","doi":"https://doi.org/10.1109/cicc.2019.8780267","mag":"2964620109"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2019.8780267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2019.8780267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024702898","display_name":"Alvin L. S. Loke","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Alvin L.S. Loke","raw_affiliation_strings":["Qualcomm, San Diego, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, San Diego, CA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013504776","display_name":"C.K. Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.K. Lee","raw_affiliation_strings":["Qualcomm, San Diego, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, San Diego, CA","institution_ids":["https://openalex.org/I4210087596"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073569808","display_name":"Burton M. Leary","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Mike Leary","raw_affiliation_strings":["Qualcomm, San Diego, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, San Diego, CA","institution_ids":["https://openalex.org/I4210087596"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5024702898"],"corresponding_institution_ids":["https://openalex.org/I4210087596"],"apc_list":null,"apc_paid":null,"fwci":0.8476,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.74363278,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"57"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7679972648620605},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.7038537263870239},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5825856328010559},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5514423251152039},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.544729471206665},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5412617921829224},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47463592886924744},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4720474183559418},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.47029396891593933},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.46846574544906616},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.45763447880744934},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.4435500502586365},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.377396821975708},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3651336431503296},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3195691704750061},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2775508165359497},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.19386136531829834}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7679972648620605},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.7038537263870239},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5825856328010559},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5514423251152039},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.544729471206665},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5412617921829224},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47463592886924744},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4720474183559418},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.47029396891593933},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.46846574544906616},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.45763447880744934},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.4435500502586365},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.377396821975708},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3651336431503296},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3195691704750061},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2775508165359497},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.19386136531829834},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2019.8780267","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2019.8780267","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5600000023841858}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":31,"referenced_works":["https://openalex.org/W1560300163","https://openalex.org/W1974338211","https://openalex.org/W2015428081","https://openalex.org/W2021819509","https://openalex.org/W2034719043","https://openalex.org/W2044443802","https://openalex.org/W2079766271","https://openalex.org/W2095296441","https://openalex.org/W2097207701","https://openalex.org/W2098569223","https://openalex.org/W2111765082","https://openalex.org/W2120475991","https://openalex.org/W2133201500","https://openalex.org/W2133800303","https://openalex.org/W2137440475","https://openalex.org/W2141369310","https://openalex.org/W2145117826","https://openalex.org/W2152224839","https://openalex.org/W2157347133","https://openalex.org/W2162517322","https://openalex.org/W2292498009","https://openalex.org/W2464059327","https://openalex.org/W2523846205","https://openalex.org/W2526988581","https://openalex.org/W2536886358","https://openalex.org/W2584298940","https://openalex.org/W2593061314","https://openalex.org/W2742997206","https://openalex.org/W2787310733","https://openalex.org/W2801370963","https://openalex.org/W2802784419"],"related_works":["https://openalex.org/W2051886008","https://openalex.org/W2059530328","https://openalex.org/W3011978806","https://openalex.org/W2743305891","https://openalex.org/W3205162826","https://openalex.org/W3207169898","https://openalex.org/W3198354237","https://openalex.org/W2110634429","https://openalex.org/W2951650892","https://openalex.org/W4242619554"],"abstract_inverted_index":{"AMS":[0,13,36,45],"design":[1,37,46,54],"in":[2],"remaining":[3],"CMOS":[4],"nodes":[5],"is":[6],"tedious":[7],"&":[8,23,42],"about":[9],"managing":[10],"technology-imposed":[11],"non-idealities.":[12],"area":[14],"scaling":[15],"0.8-0.9x":[16],"per":[17],"node":[18],"vs.":[19],"0.5x":[20],"for":[21],"logic":[22],"SRAM.":[24],"Parasitics":[25],"a":[26],"LDEs":[27],"only":[28],"get":[29],"worse,":[30],"will":[31],"ultimately":[32],"limit":[33],"scaling.":[34],"Digital-friendly":[35],"inspires":[38],"new":[39],"performance,":[40],"power":[41],"integration":[43],"levels.":[44],"at":[47],"inflection":[48],"towards":[49],"more":[50],"automation":[51],"to":[52],"reduce":[53],"iterations.":[55]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":4},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1}],"updated_date":"2026-05-08T15:41:06.802602","created_date":"2025-10-10T00:00:00"}