{"id":"https://openalex.org/W2802791498","doi":"https://doi.org/10.1109/cicc.2018.8357110","title":"Hybrid PLL architectures and implementations","display_name":"Hybrid PLL architectures and implementations","publication_year":2018,"publication_date":"2018-04-01","ids":{"openalex":"https://openalex.org/W2802791498","doi":"https://doi.org/10.1109/cicc.2018.8357110","mag":"2802791498"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2018.8357110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2018.8357110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004166346","display_name":"Daniel J. Friedman","orcid":"https://orcid.org/0000-0002-3967-8746"},"institutions":[{"id":"https://openalex.org/I114027177","display_name":"University of North Carolina at Chapel Hill","ror":"https://ror.org/0130frc33","country_code":"US","type":"education","lineage":["https://openalex.org/I114027177"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Daniel Friedman","raw_affiliation_strings":["Department of Computer Science, University of North Carolina at Chapel Hill, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of North Carolina at Chapel Hill, USA","institution_ids":["https://openalex.org/I114027177"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5004166346"],"corresponding_institution_ids":["https://openalex.org/I114027177"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04222477,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"43","issue":null,"first_page":"1","last_page":"89"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.995199978351593,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.9197347164154053},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6741849780082703},{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.5892404913902283},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5889247059822083},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5569041967391968},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.5399757027626038},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5220582485198975},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.5003290176391602},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.4748121500015259},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4396759271621704},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4132084250450134},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3907943367958069},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1760992705821991}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.9197347164154053},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6741849780082703},{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.5892404913902283},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5889247059822083},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5569041967391968},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.5399757027626038},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5220582485198975},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.5003290176391602},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.4748121500015259},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4396759271621704},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4132084250450134},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3907943367958069},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1760992705821991},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2018.8357110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2018.8357110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1964341337","https://openalex.org/W1991259611","https://openalex.org/W2005123963","https://openalex.org/W2030871918","https://openalex.org/W2041008635","https://openalex.org/W2084541386","https://openalex.org/W2094654792","https://openalex.org/W2104643154","https://openalex.org/W2105386586","https://openalex.org/W2108185796","https://openalex.org/W2120500930","https://openalex.org/W2133379964","https://openalex.org/W2144581882","https://openalex.org/W2145361466","https://openalex.org/W2146298723","https://openalex.org/W2146606114","https://openalex.org/W2148017713","https://openalex.org/W2150783292","https://openalex.org/W2153293882","https://openalex.org/W2161421010","https://openalex.org/W2166268103","https://openalex.org/W2180930247","https://openalex.org/W3142120744","https://openalex.org/W4285719527","https://openalex.org/W6658145082","https://openalex.org/W6672080346","https://openalex.org/W6675248191","https://openalex.org/W6681887207"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W984417604","https://openalex.org/W2498262093","https://openalex.org/W2474043983","https://openalex.org/W2544336511","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W1978186604","https://openalex.org/W2144737022","https://openalex.org/W2124954209"],"abstract_inverted_index":{"Initial":[0],"High":[1],"Performance":[2],"Hybrid":[3],"PLL":[4,13,31,46],"Implementation":[5],"Key":[6],"results":[7],"A":[8],"28GHz,":[9],"low":[10],"noise":[11],"hybrid":[12,63],"drawing":[14],"31mW":[15],"from":[16],"1V":[17],"demonstrated":[18],"in":[19],"32nm":[20],"CMOS":[21],"Compact,":[22],"digital":[23,30],"friendly":[24],"implementation":[25,53],"comparable":[26],"to":[27,41],"that":[28,42],"of":[29,43],"achieved":[32,47],"Linear":[33],"phase":[34],"response":[35],"and":[36],"spurious":[37],"spectral":[38],"content":[39],"similar":[40],"all":[44],"analog":[45],"Challenges":[48],"Integral":[49],"path":[50],"redundant":[51],"numbering":[52],"still":[54],"problematic":[55],"Does":[56],"not":[57],"really":[58],"exploit":[59],"opportunities":[60],"presented":[61],"by":[62],"architecture.":[64]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}