{"id":"https://openalex.org/W2174444600","doi":"https://doi.org/10.1109/cicc.2015.7338447","title":"A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer","display_name":"A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer","publication_year":2015,"publication_date":"2015-09-01","ids":{"openalex":"https://openalex.org/W2174444600","doi":"https://doi.org/10.1109/cicc.2015.7338447","mag":"2174444600"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2015.7338447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2015.7338447","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070371129","display_name":"Jie Lin","orcid":"https://orcid.org/0000-0003-3476-110X"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Jie Lin","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102166148","display_name":"Shikai Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shikai Zhu","raw_affiliation_strings":["State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109151274","display_name":"Zhiyi Yu","orcid":null},"institutions":[{"id":"https://openalex.org/I157773358","display_name":"Sun Yat-sen University","ror":"https://ror.org/0064kty71","country_code":"CN","type":"education","lineage":["https://openalex.org/I157773358"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210129003","display_name":"SYSU-CMU International Joint Research Institute","ror":"https://ror.org/02w30ae27","country_code":"CN","type":"facility","lineage":["https://openalex.org/I4210129003"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyi Yu","raw_affiliation_strings":["SYSU-CMU Joint Institute of Engineering, Sun Yat-sen University, Guangzhou, P. R. China","State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"SYSU-CMU Joint Institute of Engineering, Sun Yat-sen University, Guangzhou, P. R. China","institution_ids":["https://openalex.org/I4210129003","https://openalex.org/I157773358"]},{"raw_affiliation_string":"State Key Lab of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012524486","display_name":"Dongjun Xu","orcid":"https://orcid.org/0000-0002-1870-1740"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Dongjun Xu","raw_affiliation_strings":["School of EEE, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of EEE, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110449371","display_name":"P Manoj","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"P. D. Sai Manoj","raw_affiliation_strings":["School of EEE, Nanyang Technological University, 639798, Singapore"],"affiliations":[{"raw_affiliation_string":"School of EEE, Nanyang Technological University, 639798, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100432170","display_name":"Hao Yu","orcid":"https://orcid.org/0000-0001-8747-3203"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Hao Yu","raw_affiliation_strings":["School of EEE, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of EEE, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5070371129"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.7891,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.76555864,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.738354504108429},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7088937759399414},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6708393096923828},{"id":"https://openalex.org/keywords/serdes","display_name":"SerDes","score":0.6248713731765747},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5392485857009888},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5339381098747253},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4981865882873535},{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.46121346950531006},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4608326554298401},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42470836639404297},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3365755081176758},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.28316348791122437},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.19819536805152893},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15579834580421448}],"concepts":[{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.738354504108429},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7088937759399414},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6708393096923828},{"id":"https://openalex.org/C19707634","wikidata":"https://www.wikidata.org/wiki/Q6510662","display_name":"SerDes","level":2,"score":0.6248713731765747},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5392485857009888},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5339381098747253},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4981865882873535},{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.46121346950531006},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4608326554298401},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42470836639404297},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3365755081176758},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.28316348791122437},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.19819536805152893},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15579834580421448}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2015.7338447","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2015.7338447","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7900000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332195","display_name":"Samsung","ror":"https://ror.org/04w3jy968"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1999085092","https://openalex.org/W2005442397","https://openalex.org/W2015912445","https://openalex.org/W2036216970","https://openalex.org/W2047642791","https://openalex.org/W2087780145","https://openalex.org/W2096370786","https://openalex.org/W2114542420","https://openalex.org/W6672586714","https://openalex.org/W6674299956"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2145876553","https://openalex.org/W2146343568","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2013643406","https://openalex.org/W3012895752","https://openalex.org/W3023876411","https://openalex.org/W123152114"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,15,21,59,87],"novel":[4],"2.5D":[5,88],"multicore":[6],"processor":[7,16,94],"which":[8],"consists":[9],"of":[10,72,80,91],"3":[11],"distinct":[12],"silicon":[13],"dies:":[14],"die":[17,28,67],"with":[18,64,108],"8":[19],"MIPS-cores,":[20],"16kB":[22],"SRAM":[23],"die,":[24],"and":[25,31,50,61,101],"an":[26],"accelerator":[27],"for":[29,78],"multimedia":[30],"communication":[32,84],"applications.":[33],"These":[34],"dies":[35],"are":[36],"interconnected":[37],"into":[38],"multi-modes,":[39],"like":[40],"core-core":[41],"(up":[42],"to":[43,57],"32":[44],"cores),":[45],"core-memory":[46],"(4x":[47],"storage":[48],"capacity)":[49],"core-accelerator":[51],"(4.4x":[52],"speedup":[53],"in":[54,97],"H.264":[55],"decoder),":[56],"establish":[58],"scalable":[60],"reconfigurable":[62],"platform":[63],"less":[65],"tape-out":[66],"area":[68],"cost.":[69],"A":[70],"pair":[71],"8Gbps":[73],"SerDes":[74],"is":[75],"custom":[76],"designed":[77],"each":[79],"the":[81],"12":[82],"inter-die":[83],"channels,":[85],"achieving":[86],"I/O":[89],"bandwidth":[90],"24GB/s.":[92],"The":[93],"was":[95],"implemented":[96],"GF":[98],"65nm":[99],"process,":[100],"operates":[102],"at":[103],"500MHz":[104],"under":[105],"1.2V":[106],"supply,":[107],"1.08W":[109],"power":[110],"dissipation.":[111]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}