{"id":"https://openalex.org/W2134071101","doi":"https://doi.org/10.1109/cicc.2013.6658541","title":"How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core","display_name":"How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2134071101","doi":"https://doi.org/10.1109/cicc.2013.6658541","mag":"2134071101"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2013.6658541","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658541","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036856363","display_name":"Moongon Jung","orcid":"https://orcid.org/0000-0003-1059-2823"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Moongon Jung","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032455044","display_name":"Taigon Song","orcid":"https://orcid.org/0000-0001-5243-4132"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Taigon Song","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102094321","display_name":"Yang Wan","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yang Wan","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101399645","display_name":"Young\u2010Joon Lee","orcid":"https://orcid.org/0000-0002-1735-3385"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Young-Joon Lee","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106083836","display_name":"Debabrata Mohapatra","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debabrata Mohapatra","raw_affiliation_strings":["Intel, Intel Labs, Santa Clara, CA, USA","Intel Labs, Intel, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100370891","display_name":"Hong Wang","orcid":"https://orcid.org/0000-0002-0213-3523"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["Intel, Intel Labs, Santa Clara, CA, USA","Intel Labs, Intel, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Intel, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113819120","display_name":"G. Taylor","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Greg Taylor","raw_affiliation_strings":["Intel, Intel Labs, Hillsboro, OR, USA","Intel Labs., Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel, Intel Labs, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs., Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082212703","display_name":"Devang Jariwala","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Devang Jariwala","raw_affiliation_strings":["Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","Technol. & Manuf. Group, Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technol. & Manuf. Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038626306","display_name":"V. Pitchumani","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vijay Pitchumani","raw_affiliation_strings":["Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","Technol. & Manuf. Group, Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technol. & Manuf. Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073551639","display_name":"Patrick Morrow","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Patrick Morrow","raw_affiliation_strings":["Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","Technol. & Manuf. Group, Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technol. & Manuf. Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049160185","display_name":"Clair Webb","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Clair Webb","raw_affiliation_strings":["Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","Technol. & Manuf. Group, Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technol. & Manuf. Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103179708","display_name":"P. Fischer","orcid":"https://orcid.org/0009-0007-7797-2851"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Fischer","raw_affiliation_strings":["Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","Technol. & Manuf. Group, Intel, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology and Manufacturing Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Technol. & Manuf. Group, Intel, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052950521","display_name":"Sung Kyu Lim","orcid":"https://orcid.org/0000-0002-2267-5282"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sung Kyu Lim","raw_affiliation_strings":["School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of ECE, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"[Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA]","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":5.6742,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.97253013,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9941999912261963,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10623","display_name":"Thin-Film Transistor Technologies","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.7416665554046631},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5957709550857544},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.5707787871360779},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5681972503662109},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5652380585670471},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5624361038208008},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5551632046699524},{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.5011594295501709},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4889761209487915},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.48149263858795166},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.47615763545036316},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47574493288993835},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.47345679998397827},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4457045793533325},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.42223870754241943},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.4151952266693115},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.25752124190330505},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23445230722427368},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18810221552848816},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.10836288332939148},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1013529896736145},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08015108108520508}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.7416665554046631},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5957709550857544},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.5707787871360779},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5681972503662109},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5652380585670471},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5624361038208008},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5551632046699524},{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.5011594295501709},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4889761209487915},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.48149263858795166},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.47615763545036316},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47574493288993835},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.47345679998397827},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4457045793533325},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.42223870754241943},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.4151952266693115},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.25752124190330505},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23445230722427368},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18810221552848816},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.10836288332939148},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1013529896736145},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08015108108520508},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2013.6658541","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658541","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2027712195","https://openalex.org/W2031235329","https://openalex.org/W2048927144","https://openalex.org/W2107304970","https://openalex.org/W2143807959","https://openalex.org/W6681475522"],"related_works":["https://openalex.org/W2076263604","https://openalex.org/W2028082191","https://openalex.org/W2886805502","https://openalex.org/W1965050610","https://openalex.org/W2994788014","https://openalex.org/W2809933636","https://openalex.org/W1990789187","https://openalex.org/W2032655623","https://openalex.org/W2158921969","https://openalex.org/W2021320789"],"abstract_inverted_index":{"Low":[0],"power":[1,25,38,54,109],"is":[2],"considered":[3],"by":[4],"many":[5],"as":[6],"the":[7,112,116],"driving":[8],"force":[9],"for":[10,72],"3D":[11,27,41,57,65,91],"ICs,":[12,58],"yet":[13],"there":[14],"have":[15],"been":[16],"few":[17],"thorough":[18],"design":[19,34,60],"studies":[20],"on":[21],"how":[22],"to":[23,36,95],"reduce":[24,37],"in":[26,40,56],"ICs.":[28],"In":[29],"this":[30],"paper,":[31],"we":[32],"discuss":[33],"methodologies":[35],"consumption":[39],"IC":[42],"designs":[43,92],"using":[44],"a":[45],"commercial-grade":[46],"CPU":[47],"core":[48],"(OpenSPARC":[49],"T2":[50],"core).":[51],"To":[52],"demonstrate":[53],"benefits":[55],"four":[59],"techniques":[61],"are":[62],"explored:":[63],"(1)":[64],"floorplanning,":[66],"(2)":[67],"metal":[68],"layer":[69],"usage":[70],"control":[71],"intra-block-level":[73],"routing,":[74],"(3)":[75],"dual-Vth":[76],"design,":[77],"and":[78,107],"(4)":[79],"functional":[80],"unit":[81],"block":[82],"(FUB)":[83],"folding.":[84],"With":[85],"aforementioned":[86],"methods":[87],"combined,":[88],"our":[89],"2-tier":[90],"provide":[93],"up":[94],"52.3%":[96],"reduced":[97],"footprint,":[98],"25.5%":[99],"shorter":[100],"wirelength,":[101],"30.2%":[102],"decreased":[103],"buffer":[104],"cell":[105],"count,":[106],"21.2%":[108],"reduction":[110],"over":[111],"2D":[113],"counterpart":[114],"under":[115],"same":[117],"performance.":[118]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":8},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
