{"id":"https://openalex.org/W2058444412","doi":"https://doi.org/10.1109/cicc.2013.6658490","title":"Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering","display_name":"Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2058444412","doi":"https://doi.org/10.1109/cicc.2013.6658490","mag":"2058444412"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2013.6658490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658490","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100741945","display_name":"Guanhua Wang","orcid":"https://orcid.org/0000-0001-6130-8496"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Guanhua Wang","raw_affiliation_strings":["Analog and Mixed-Signal Lab, University of Texas at Dallas, Richardson, TX, USA","Texas Analog Center of Excellence, Univ. of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Analog and Mixed-Signal Lab, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Texas Analog Center of Excellence, Univ. of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047697146","display_name":"Yun Chiu","orcid":"https://orcid.org/0000-0001-5239-4417"},"institutions":[{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yun Chiu","raw_affiliation_strings":["Analog and Mixed-Signal Lab, University of Texas at Dallas, Richardson, TX, USA","Texas Analog Center of Excellence, Univ. of Texas at Dallas, Richardson, TX, USA"],"affiliations":[{"raw_affiliation_string":"Analog and Mixed-Signal Lab, University of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]},{"raw_affiliation_string":"Texas Analog Center of Excellence, Univ. of Texas at Dallas, Richardson, TX, USA","institution_ids":["https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5100741945"],"corresponding_institution_ids":["https://openalex.org/I162577319"],"apc_list":null,"apc_paid":null,"fwci":0.3997,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64689092,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/emulation","display_name":"Emulation","score":0.7414175271987915},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7280334234237671},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7193299531936646},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5255329012870789},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.5085076093673706},{"id":"https://openalex.org/keywords/hardware-emulation","display_name":"Hardware emulation","score":0.5035483241081238},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.4994041919708252},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.41490232944488525},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3760288655757904},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.2047596275806427},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.17561963200569153},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11349731683731079}],"concepts":[{"id":"https://openalex.org/C149810388","wikidata":"https://www.wikidata.org/wiki/Q5374873","display_name":"Emulation","level":2,"score":0.7414175271987915},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7280334234237671},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7193299531936646},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5255329012870789},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.5085076093673706},{"id":"https://openalex.org/C94115699","wikidata":"https://www.wikidata.org/wiki/Q5656406","display_name":"Hardware emulation","level":3,"score":0.5035483241081238},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.4994041919708252},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.41490232944488525},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3760288655757904},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.2047596275806427},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.17561963200569153},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11349731683731079},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C50522688","wikidata":"https://www.wikidata.org/wiki/Q189833","display_name":"Economic growth","level":1,"score":0.0},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2013.6658490","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658490","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1570682605","https://openalex.org/W1939837620","https://openalex.org/W2007472976","https://openalex.org/W2032844593","https://openalex.org/W2078717740","https://openalex.org/W2084403776","https://openalex.org/W2088635916","https://openalex.org/W2102149886","https://openalex.org/W2109283493","https://openalex.org/W2110612653","https://openalex.org/W2117638260","https://openalex.org/W3148484537","https://openalex.org/W6634058547","https://openalex.org/W6669496447"],"related_works":["https://openalex.org/W2170071008","https://openalex.org/W1995865860","https://openalex.org/W2103996454","https://openalex.org/W2106791114","https://openalex.org/W3029775214","https://openalex.org/W2390650884","https://openalex.org/W2093057572","https://openalex.org/W2001552871","https://openalex.org/W1974143443","https://openalex.org/W2353557016"],"abstract_inverted_index":{"A":[0],"custom":[1],"FPGA":[2,64],"emulation":[3,65],"platform":[4],"for":[5,15,37,70],"the":[6,38,63,71],"verification":[7],"of":[8,31,40],"a":[9,32,46,67,76],"slowly":[10],"adapted,":[11],"background":[12,57],"calibration":[13],"technique":[14],"successive-approximation-register":[16],"(SAR)":[17],"analog-to-digital":[18],"converter":[19],"(ADC)":[20],"is":[21,35],"demonstrated":[22],"in":[23,45],"an":[24],"Altera":[25],"DE4":[26],"board.":[27],"The":[28],"internal":[29],"redundancy":[30],"sub-binary":[33],"SAR":[34,48],"exploited":[36],"identification":[39],"ten":[41],"leading":[42],"bit":[43,52],"weights":[44],"14.5-bit":[47],"ADC":[49],"using":[50],"pseudorandom":[51],"sequence":[53],"(PRBS)":[54],"injection":[55],"with":[56],"correlation.":[58],"Experimental":[59],"results":[60],"reveal":[61],"that":[62],"achieves":[66],"3000\u00d7":[68],"speedup":[69],"same":[72],"simulation":[73],"executed":[74],"on":[75],"general-purpose":[77],"microprocessor.":[78]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
