{"id":"https://openalex.org/W2008240724","doi":"https://doi.org/10.1109/cicc.2013.6658437","title":"Distributed clock generator for synchronous SoC using ADPLL network","display_name":"Distributed clock generator for synchronous SoC using ADPLL network","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2008240724","doi":"https://doi.org/10.1109/cicc.2013.6658437","mag":"2008240724"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2013.6658437","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000777718","display_name":"Eldar Zianbetov","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"E. Zianbetov","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109189243","display_name":"J. M. Akre","orcid":null},"institutions":[{"id":"https://openalex.org/I102475099","display_name":"Sup\u00e9lec","ror":"https://ror.org/00n7gwn90","country_code":"FR","type":"education","lineage":["https://openalex.org/I102475099"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J- M. Akre","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]},{"raw_affiliation_string":"E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)","institution_ids":["https://openalex.org/I102475099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111818698","display_name":"J. Juillard","orcid":null},"institutions":[{"id":"https://openalex.org/I102475099","display_name":"Sup\u00e9lec","ror":"https://ror.org/00n7gwn90","country_code":"FR","type":"education","lineage":["https://openalex.org/I102475099"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J. Juillard","raw_affiliation_strings":["Sup\u00e9lec, Gif-Sur-Yvette, France","E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sup\u00e9lec, Gif-Sur-Yvette, France","institution_ids":["https://openalex.org/I102475099"]},{"raw_affiliation_string":"E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)","institution_ids":["https://openalex.org/I102475099"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032777255","display_name":"Dimitri Galayko","orcid":"https://orcid.org/0000-0002-7056-7489"},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"D. Galayko","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112858873","display_name":"Fran\u00e7ois Anceau","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"F. Anceau","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072777783","display_name":"Mohammad Mahdi Javidan","orcid":"https://orcid.org/0000-0002-1206-0575"},"institutions":[{"id":"https://openalex.org/I102475099","display_name":"Sup\u00e9lec","ror":"https://ror.org/00n7gwn90","country_code":"FR","type":"education","lineage":["https://openalex.org/I102475099"]},{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"M. Javidan","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"E3S - Sup\u00e9lec Sciences des Syst\u00e8mes (Plateau du Moulon - 3 rue Joliot-Curie  -  91192 GIF-SUR-YVETTE CEDEX - France)","institution_ids":["https://openalex.org/I102475099"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108422992","display_name":"C. Shan","orcid":null},"institutions":[{"id":"https://openalex.org/I39804081","display_name":"Sorbonne Universit\u00e9","ror":"https://ror.org/02en5vm52","country_code":"FR","type":"education","lineage":["https://openalex.org/I39804081"]},{"id":"https://openalex.org/I4210159731","display_name":"LIP6","ror":"https://ror.org/05krcen59","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I39804081","https://openalex.org/I4210159245","https://openalex.org/I4210159731"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"C. Shan","raw_affiliation_strings":["UPMC, LIP6 lab, Paris, France","CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"UPMC, LIP6 lab, Paris, France","institution_ids":["https://openalex.org/I39804081","https://openalex.org/I4210159731"]},{"raw_affiliation_string":"CIAN - Circuits Int\u00e9gr\u00e9s Num\u00e9riques et Analogiques (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073233302","display_name":"Olivier Billoint","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I3020098449","display_name":"CEA Grenoble","ror":"https://ror.org/02mg6n827","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I3020098449"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"O. Billoint","raw_affiliation_strings":["CEA-LETI, Grenoble, France","CEA-LETI - Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEA-LETI, Grenoble, France","institution_ids":["https://openalex.org/I2738703131","https://openalex.org/I3020098449","https://openalex.org/I4210150049"]},{"raw_affiliation_string":"CEA-LETI - Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I2738703131","https://openalex.org/I3020098449","https://openalex.org/I4210150049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021075726","display_name":"Anton Korniienko","orcid":"https://orcid.org/0000-0002-4732-4470"},"institutions":[{"id":"https://openalex.org/I4210145913","display_name":"Laboratoire Amp\u00e8re","ror":"https://ror.org/04xbczw40","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I4210145913","https://openalex.org/I48430043"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. Korniienko","raw_affiliation_strings":["Amp\u00e9re lab, Lyon, France","MIS - Amp\u00e8re, D\u00e9partement M\u00e9thodes pour l'Ing\u00e9nierie des Syst\u00e8mes (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Amp\u00e9re lab, Lyon, France","institution_ids":["https://openalex.org/I4210145913"]},{"raw_affiliation_string":"MIS - Amp\u00e8re, D\u00e9partement M\u00e9thodes pour l'Ing\u00e9nierie des Syst\u00e8mes (France)","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105835303","display_name":"E. Colinet","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I2738703131","display_name":"Commissariat \u00e0 l'\u00c9nergie Atomique et aux \u00c9nergies Alternatives","ror":"https://ror.org/00jjx8s55","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131"]},{"id":"https://openalex.org/I3020098449","display_name":"CEA Grenoble","ror":"https://ror.org/02mg6n827","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I3020098449"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"E. Colinet","raw_affiliation_strings":["CEA-LETI, Grenoble, France","CEA-LETI - Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"CEA-LETI, Grenoble, France","institution_ids":["https://openalex.org/I2738703131","https://openalex.org/I3020098449","https://openalex.org/I4210150049"]},{"raw_affiliation_string":"CEA-LETI - Commissariat \u00e0 l'\u00e9nergie atomique et aux \u00e9nergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (MINATEC 17, rue des Martyrs, 38054, Grenoble Cedex 9 - France)","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I2738703131","https://openalex.org/I3020098449","https://openalex.org/I4210150049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5001215062","display_name":"G\u00e9rard Scorletti","orcid":"https://orcid.org/0000-0001-5083-0879"},"institutions":[{"id":"https://openalex.org/I4210145913","display_name":"Laboratoire Amp\u00e8re","ror":"https://ror.org/04xbczw40","country_code":"FR","type":"facility","lineage":["https://openalex.org/I100532134","https://openalex.org/I112936343","https://openalex.org/I1294671590","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I203339264","https://openalex.org/I4210145913","https://openalex.org/I48430043"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Scorletti","raw_affiliation_strings":["Amp\u00e9re lab, Lyon, France","MIS - Amp\u00e8re, D\u00e9partement M\u00e9thodes pour l'Ing\u00e9nierie des Syst\u00e8mes (France)"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Amp\u00e9re lab, Lyon, France","institution_ids":["https://openalex.org/I4210145913"]},{"raw_affiliation_string":"MIS - Amp\u00e8re, D\u00e9partement M\u00e9thodes pour l'Ing\u00e9nierie des Syst\u00e8mes (France)","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":true,"cited_by_count":16,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.822940468788147},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.7629281282424927},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6998521089553833},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.6780117750167847},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5930972695350647},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.5754624009132385},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5253797769546509},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.5150167942047119},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47474509477615356},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.4724987745285034},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.46263712644577026},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4273899495601654},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.4164665937423706},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41210705041885376},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.41079068183898926},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34568357467651367},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.331190288066864},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.29577669501304626},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.24632084369659424},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18551868200302124},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10048490762710571}],"concepts":[{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.822940468788147},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.7629281282424927},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6998521089553833},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.6780117750167847},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5930972695350647},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.5754624009132385},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5253797769546509},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.5150167942047119},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47474509477615356},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.4724987745285034},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.46263712644577026},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4273899495601654},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.4164665937423706},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41210705041885376},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.41079068183898926},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34568357467651367},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.331190288066864},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.29577669501304626},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.24632084369659424},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18551868200302124},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10048490762710571},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/cicc.2013.6658437","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2013.6658437","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2013 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.635.4371","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.635.4371","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://hal.upmc.fr/docs/01/05/37/68/PDF/cicc2013_pll_network.pdf","raw_type":"text"},{"id":"pmh:oai:HAL:hal-01053768v1","is_oa":false,"landing_page_url":"https://hal.sorbonne-universite.fr/hal-01053768","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"CICC 2013 - IEEE 2013 Custom Integrated Circuits Conference, Sep 2013, San Jos\u00e9, CA, United States. pp.1-4, &#x27E8;10.1109/CICC.2013.6658437&#x27E9;","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.75}],"awards":[{"id":"https://openalex.org/G563897223","display_name":null,"funder_award_id":"ANR-10-SEGI-0014","funder_id":"https://openalex.org/F4320320883","funder_display_name":"Agence Nationale de la Recherche"}],"funders":[{"id":"https://openalex.org/F4320320883","display_name":"Agence Nationale de la Recherche","ror":"https://ror.org/00rbzpz17"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2026006738","https://openalex.org/W2037306258","https://openalex.org/W2082715750","https://openalex.org/W2097242029","https://openalex.org/W2108185796","https://openalex.org/W2111991111","https://openalex.org/W2118232269","https://openalex.org/W2119817173","https://openalex.org/W2135663303"],"related_works":["https://openalex.org/W2169622190","https://openalex.org/W2224788396","https://openalex.org/W2124909075","https://openalex.org/W2133326759","https://openalex.org/W2389820945","https://openalex.org/W3006003651","https://openalex.org/W2117541676","https://openalex.org/W1607003253","https://openalex.org/W2082030077","https://openalex.org/W2150865404"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11,32],"novel":[4],"architecture":[5,54],"of":[6,13,35,55],"on-chip":[7],"clock":[8,44],"generation":[9,57],"employing":[10],"network":[12],"oscillators":[14],"synchronized":[15],"by":[16],"the":[17,42,56],"distributed":[18],"all-digital":[19],"PLLs":[20],"(ADPLLs).":[21],"The":[22,38,51],"implemented":[23],"prototype":[24],"has":[25],"16":[26],"clocking":[27],"domains":[28,45],"operating":[29],"synchronously":[30],"in":[31,67],"frequency":[33],"range":[34],"1.1-2.4":[36],"GHz.":[37],"synchronization":[39,62],"error":[40],"between":[41],"neighboring":[43],"is":[46],"less":[47],"than":[48],"60":[49],"ps.":[50],"fully":[52],"digital":[53],"offers":[58],"flexibility":[59],"and":[60],"efficient":[61],"control":[63],"suitable":[64],"for":[65],"use":[66],"synchronous":[68],"SoCs.":[69]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-26T07:53:14.480251","created_date":"2025-10-10T00:00:00"}
