{"id":"https://openalex.org/W2124051711","doi":"https://doi.org/10.1109/cicc.2012.6330709","title":"A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS","display_name":"A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2124051711","doi":"https://doi.org/10.1109/cicc.2012.6330709","mag":"2124051711"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2012.6330709","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2012.6330709","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069007377","display_name":"Pierce Chuang","orcid":"https://orcid.org/0000-0001-5850-7048"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Pierce I-Jen Chuang","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada","University of Waterloo Waterloo, Ontario, Canada N2L 3G1"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo Waterloo, Ontario, Canada N2L 3G1","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100432958","display_name":"David Li","orcid":"https://orcid.org/0000-0002-6401-4263"},"institutions":[{"id":"https://openalex.org/I4210087596","display_name":"Qualcomm (United States)","ror":"https://ror.org/002zrf773","country_code":"US","type":"company","lineage":["https://openalex.org/I4210087596"]},{"id":"https://openalex.org/I4210111675","display_name":"Market Matters","ror":"https://ror.org/021yan307","country_code":"US","type":"nonprofit","lineage":["https://openalex.org/I4210111675"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"David Li","raw_affiliation_strings":["Qualcomm, Inc., San Diego, CA, USA","Qualcomm Inc., San Diego, CA, 92121"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Qualcomm, Inc., San Diego, CA, USA","institution_ids":["https://openalex.org/I4210087596"]},{"raw_affiliation_string":"Qualcomm Inc., San Diego, CA, 92121","institution_ids":["https://openalex.org/I4210087596","https://openalex.org/I4210111675"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086259491","display_name":"Manoj Sachdev","orcid":"https://orcid.org/0000-0002-8256-9828"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Manoj Sachdev","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada","University of Waterloo Waterloo, Ontario, Canada N2L 3G1"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo Waterloo, Ontario, Canada N2L 3G1","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024704337","display_name":"Vincent Gaudet","orcid":"https://orcid.org/0000-0002-5534-0825"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Vincent Gaudet","raw_affiliation_strings":["University of Waterloo, Waterloo, ONT, Canada","University of Waterloo Waterloo, Ontario, Canada N2L 3G1"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Waterloo, Waterloo, ONT, Canada","institution_ids":["https://openalex.org/I151746483"]},{"raw_affiliation_string":"University of Waterloo Waterloo, Ontario, Canada N2L 3G1","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.8246,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.71723381,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8900833129882812},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6503455638885498},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6363197565078735},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6230685114860535},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5947326421737671},{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.560196042060852},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5268168449401855},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.47824421525001526},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.4717220664024353},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.47107353806495667},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4256511628627777},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4045841693878174},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3240935206413269},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27636846899986267},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19919463992118835},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.16338792443275452},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.14034438133239746},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12886208295822144},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.12263917922973633},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10750019550323486}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8900833129882812},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6503455638885498},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6363197565078735},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6230685114860535},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5947326421737671},{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.560196042060852},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5268168449401855},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.47824421525001526},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.4717220664024353},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.47107353806495667},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4256511628627777},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4045841693878174},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3240935206413269},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27636846899986267},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19919463992118835},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.16338792443275452},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.14034438133239746},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12886208295822144},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.12263917922973633},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10750019550323486},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2012.6330709","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2012.6330709","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1784686638","https://openalex.org/W2053325738","https://openalex.org/W2104733895","https://openalex.org/W2105246572","https://openalex.org/W2121843607","https://openalex.org/W2136656113","https://openalex.org/W2168397038","https://openalex.org/W3149199860","https://openalex.org/W6638190493","https://openalex.org/W6680257602"],"related_works":["https://openalex.org/W2155174752","https://openalex.org/W2142702094","https://openalex.org/W2118487491","https://openalex.org/W1996543053","https://openalex.org/W2985303806","https://openalex.org/W2125567818","https://openalex.org/W2327368230","https://openalex.org/W2158157809","https://openalex.org/W1601832081","https://openalex.org/W4324145463"],"abstract_inverted_index":{"A":[0],"148ps,":[1],"single-cycle":[2],"64-bit":[3],"Ling":[4],"adder":[5],"with":[6],"Constant-Delay":[7],"(CD)":[8],"logic":[9,31,36,45,49],"implemented":[10],"in":[11,17,46],"the":[12,30],"critical":[13],"path":[14],"is":[15],"fabricated":[16],"a":[18],"65nm,":[19],"1V":[20,55],"CMOS":[21],"process.":[22],"The":[23],"pre-evaluation":[24],"and":[25,62,67],"constant":[26],"delay":[27],"(regardless":[28],"of":[29,34],"expressions)":[32],"features":[33],"CD":[35],"makes":[37],"it":[38],"up":[39],"to":[40],"2X":[41],"faster":[42],"than":[43],"dynamic":[44],"realizing":[47],"complex":[48],"functions":[50],"such":[51],"as":[52],"addition.":[53],"At":[54],"supply,":[56],"this":[57],"adder's":[58],"worst-case":[59],"measured":[60],"power":[61,64],"leakage":[63],"are":[65],"135mW":[66],"0.22mW,":[68],"respectively.":[69]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
