{"id":"https://openalex.org/W2156903694","doi":"https://doi.org/10.1109/cicc.2012.6330636","title":"SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation","display_name":"SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2156903694","doi":"https://doi.org/10.1109/cicc.2012.6330636","mag":"2156903694"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2012.6330636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2012.6330636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5049087262","display_name":"Eustace Painkras","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Eustace Painkras","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015816826","display_name":"Luis A. Plana","orcid":"https://orcid.org/0000-0002-6113-3929"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Luis A. Plana","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053098822","display_name":"Jim Garside","orcid":"https://orcid.org/0000-0001-8812-4742"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jim Garside","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047132316","display_name":"Steve Temple","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Steve Temple","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032164032","display_name":"Simon Davidson","orcid":"https://orcid.org/0000-0001-5385-442X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Simon Davidson","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024526139","display_name":"Jeffrey Pepper","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Jeffrey Pepper","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013673413","display_name":"David Clark","orcid":"https://orcid.org/0000-0002-7004-934X"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Clark","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109675287","display_name":"Cameron Patterson","orcid":null},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Cameron Patterson","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5083177159","display_name":"Steve Furber","orcid":"https://orcid.org/0000-0002-6524-3367"},"institutions":[{"id":"https://openalex.org/I28407311","display_name":"University of Manchester","ror":"https://ror.org/027m9bs27","country_code":"GB","type":"education","lineage":["https://openalex.org/I28407311"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Steve Furber","raw_affiliation_strings":["University of Manchester, UK"],"affiliations":[{"raw_affiliation_string":"University of Manchester, UK","institution_ids":["https://openalex.org/I28407311"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5049087262"],"corresponding_institution_ids":["https://openalex.org/I28407311"],"apc_list":null,"apc_paid":null,"fwci":4.4937,"has_fulltext":false,"cited_by_count":70,"citation_normalized_percentile":{"value":0.95027406,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.870124101638794},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.7712127566337585},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7659802436828613},{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.6783941388130188},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5833285450935364},{"id":"https://openalex.org/keywords/spiking-neural-network","display_name":"Spiking neural network","score":0.5772430896759033},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5743537545204163},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5546923875808716},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5479663610458374},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45227178931236267},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.44399237632751465},{"id":"https://openalex.org/keywords/network-packet","display_name":"Network packet","score":0.4348308742046356},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43040311336517334},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41647934913635254},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41613495349884033},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3812731206417084},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3506007194519043},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.32051384449005127},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.17903661727905273},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13191494345664978},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10649120807647705}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.870124101638794},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.7712127566337585},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7659802436828613},{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.6783941388130188},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5833285450935364},{"id":"https://openalex.org/C11731999","wikidata":"https://www.wikidata.org/wiki/Q9067355","display_name":"Spiking neural network","level":3,"score":0.5772430896759033},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5743537545204163},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5546923875808716},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5479663610458374},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45227178931236267},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.44399237632751465},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.4348308742046356},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43040311336517334},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41647934913635254},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41613495349884033},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3812731206417084},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3506007194519043},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.32051384449005127},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.17903661727905273},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13191494345664978},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10649120807647705},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":5,"locations":[{"id":"doi:10.1109/cicc.2012.6330636","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2012.6330636","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2012 Custom Integrated Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/efd4615b-7bb6-4d9d-899c-6aacae209fc5","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/efd4615b-7bb6-4d9d-899c-6aacae209fc5","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Painkras, E, Plana, L A, Garside, J, Temple, S, Davidson, S, Pepper, J, Clark, D, Patterson, C & Furber, S 2012, SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation. in Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf. IEEE, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, 1/07/12. https://doi.org/10.1109/CICC.2012.6330636","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.458.4033","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.458.4033","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://apt.cs.manchester.ac.uk//people/cpatterson/spinnaker_chip.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:publications/efd4615b-7bb6-4d9d-899c-6aacae209fc5","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/spinnaker-a-multicore-systemonchip-for-massivelyparallel-neural-net-simulation(efd4615b-7bb6-4d9d-899c-6aacae209fc5).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Painkras, E, Plana, L A, Garside, J, Temple, S, Davidson, S, Pepper, J, Clark, D, Patterson, C & Furber, S 2012, SpiNNaker: A multi-core system-on-chip for massively-parallel neural net simulation. in Proceedings of the Custom Integrated Circuits Conference|Proc Custom Integr Circuits Conf. IEEE, 34th Annual Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, 1/07/12. https://doi.org/10.1109/CICC.2012.6330636","raw_type":"info:eu-repo/semantics/publishedVersion"},{"id":"pmh:oai:uobrep.openrepository.com:10547/297903","is_oa":false,"landing_page_url":"http://hdl.handle.net/10547/297903","pdf_url":null,"source":{"id":"https://openalex.org/S4306400178","display_name":"University of Bedfordshire Repository (University of Bedfordshire)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I147554453","host_organization_name":"University of Bedfordshire","host_organization_lineage":["https://openalex.org/I147554453"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"Conference papers, meetings and proceedings"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5600000023841858,"id":"https://metadata.un.org/sdg/9"}],"awards":[{"id":"https://openalex.org/G323116497","display_name":null,"funder_award_id":"EP/G015740/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G7996027513","display_name":null,"funder_award_id":"EP/D079594/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"},{"id":"https://openalex.org/G8450547870","display_name":null,"funder_award_id":"EP/G015775/1","funder_id":"https://openalex.org/F4320334627","funder_display_name":"Engineering and Physical Sciences Research Council"}],"funders":[{"id":"https://openalex.org/F4320334627","display_name":"Engineering and Physical Sciences Research Council","ror":"https://ror.org/0439y7842"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1972827198","https://openalex.org/W2031273683","https://openalex.org/W2034297532","https://openalex.org/W2087058693","https://openalex.org/W2153287508","https://openalex.org/W2161311656","https://openalex.org/W2169901964","https://openalex.org/W2171471042","https://openalex.org/W4213379201"],"related_works":["https://openalex.org/W2502691491","https://openalex.org/W1976012348","https://openalex.org/W2002682434","https://openalex.org/W2137671689","https://openalex.org/W4387782849","https://openalex.org/W2113449380","https://openalex.org/W2012131147","https://openalex.org/W2157008728","https://openalex.org/W2092587530","https://openalex.org/W2016942572"],"abstract_inverted_index":{"The":[0,37,72],"modelling":[1],"of":[2,5,14,40,90,98],"large":[3],"systems":[4],"spiking":[6,32],"neurons":[7,33],"is":[8,20,43],"computationally":[9],"very":[10],"demanding":[11],"in":[12,34,61,78,114],"terms":[13],"processing":[15],"power":[16,96,122],"and":[17,93,120,123],"communication.":[18],"SpiNNaker":[19,45,110],"a":[21,30,48,66,79,87,95],"massively-parallel":[22],"computer":[23],"system":[24,54],"designed":[25],"to":[26,29],"model":[27],"up":[28],"billion":[31],"real":[35],"time.":[36],"basic":[38],"block":[39],"the":[41,44],"machine":[42],"multicore":[46],"System-on-Chip,":[47],"Globally":[49],"Asynchronous":[50],"Locally":[51],"Synchronous":[52],"(GALS)":[53],"with":[55],"18":[56],"ARM968":[57],"processor":[58,104],"nodes":[59],"residing":[60],"synchronous":[62],"islands,":[63],"surrounded":[64],"by":[65],"light-weight,":[67],"packet-switched":[68],"asynchronous":[69],"communications":[70],"infrastructure.":[71],"MPSoC":[73],"contains":[74],"100":[75],"million":[76],"transistors":[77],"102":[80],"mm":[81],"<sup":[82],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[83],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[84],"die,":[85],"provides":[86],"peak":[88],"performance":[89,124],"3.96":[91],"GIPS":[92],"has":[94],"consumption":[97],"1W":[99],"at":[100,107],"1.2V":[101],"when":[102],"all":[103],"cores":[105],"operate":[106],"nominal":[108],"frequency.":[109],"chips":[111],"were":[112,117],"delivered":[113],"May":[115],"2011,":[116],"fully":[118],"operational,":[119],"met":[121],"requirements.":[125]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":9},{"year":2021,"cited_by_count":7},{"year":2020,"cited_by_count":5},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":5},{"year":2016,"cited_by_count":4},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":8},{"year":2013,"cited_by_count":5},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
