{"id":"https://openalex.org/W2104810822","doi":"https://doi.org/10.1109/cicc.2011.6055417","title":"An at-speed self-testable technique for the high speed domino adder","display_name":"An at-speed self-testable technique for the high speed domino adder","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2104810822","doi":"https://doi.org/10.1109/cicc.2011.6055417","mag":"2104810822"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2011.6055417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2011.6055417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038670362","display_name":"Yushun Wang","orcid":"https://orcid.org/0000-0002-6200-220X"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Shun Wang","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112029971","display_name":"Min-Han Hsieh","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Min-Han Hsieh","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055814161","display_name":"Chia\u2010Ming Liu","orcid":"https://orcid.org/0000-0003-1752-9261"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chia-Ming Liu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101508754","display_name":"Chi\u2010Wei Liu","orcid":"https://orcid.org/0009-0000-3201-5141"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Wei Liu","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005153073","display_name":"James C. M. Li","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"James C.-M. Li","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110214866","display_name":"Charlie Chung\u2010Ping Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Charlie Chung-Ping Chen","raw_affiliation_strings":["Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Graduate Institute of Electronics Engineering, National Taiwan University Taipei, Taiwan 10617, R.O.C","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.5153,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.67912027,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"519","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9151247143745422},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7396156787872314},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.7220708131790161},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7176532745361328},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6554262638092041},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5739659667015076},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.4465934634208679},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41953787207603455},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4040682911872864},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3953297734260559},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3507853150367737},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.25504711270332336},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13364648818969727},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11044740676879883},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07526275515556335}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9151247143745422},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7396156787872314},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.7220708131790161},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7176532745361328},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6554262638092041},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5739659667015076},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.4465934634208679},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41953787207603455},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4040682911872864},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3953297734260559},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3507853150367737},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.25504711270332336},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13364648818969727},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11044740676879883},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07526275515556335},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2011.6055417","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2011.6055417","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE Custom Integrated Circuits Conference (CICC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7200000286102295,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W2031234016","https://openalex.org/W2031967364","https://openalex.org/W2043949919","https://openalex.org/W2053325738","https://openalex.org/W2061946964","https://openalex.org/W2065318410","https://openalex.org/W2065379887","https://openalex.org/W2096207794","https://openalex.org/W2097414281","https://openalex.org/W2102127226","https://openalex.org/W2128202363","https://openalex.org/W2137636909","https://openalex.org/W2152321821","https://openalex.org/W2170615965","https://openalex.org/W4252770414","https://openalex.org/W6658668434","https://openalex.org/W6678988370","https://openalex.org/W6834746897"],"related_works":["https://openalex.org/W4231158717","https://openalex.org/W2059009651","https://openalex.org/W3174071739","https://openalex.org/W2150513440","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2098328611","https://openalex.org/W2100009051","https://openalex.org/W2168226525","https://openalex.org/W2025555754"],"abstract_inverted_index":{"An":[0],"at-speed":[1,71],"self-testable":[2],"technique":[3,48,66],"is":[4,34,49,67],"proposed":[5,47],"for":[6,70],"the":[7,22,38],"high":[8,77],"speed":[9,74],"domino":[10,55],"adder.":[11],"We":[12],"apply":[13],"pseudo-exhaustive":[14],"testing":[15,72],"so":[16],"that":[17],"all":[18],"testable":[19],"faults":[20],"in":[21,60],"64-bit":[23,54],"adder":[24,32,56],"are":[25],"detected":[26],"by":[27,37],"just":[28],"23K":[29],"patterns.":[30],"The":[31,46],"latency":[33,59],"accurately":[35],"measured":[36],"programmable-skew":[39],"clock":[40],"generated":[41],"from":[42],"delay-locked":[43],"loop":[44],"(DLL).":[45],"validated":[50],"on":[51],"a":[52],"6.4GHz":[53],"with":[57],"181ps":[58],"90nm":[61],"CMOS":[62],"technology.":[63],"This":[64],"on-chip":[65],"very":[68],"useful":[69],"and":[73],"binning":[75],"of":[76],"performance":[78],"CPU.":[79]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}