{"id":"https://openalex.org/W2140854523","doi":"https://doi.org/10.1109/cicc.2009.5280873","title":"64-bit prefix adders: Power-efficient topologies and design solutions","display_name":"64-bit prefix adders: Power-efficient topologies and design solutions","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2140854523","doi":"https://doi.org/10.1109/cicc.2009.5280873","mag":"2140854523"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2009.5280873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026584653","display_name":"Ching Zhou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Ching Zhou","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM T. J. Watson Research Center, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J. Watson Research Center, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072965417","display_name":"Bruce Fleischer","orcid":"https://orcid.org/0000-0002-7033-1564"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bruce M. Fleischer","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM T. J. Watson Research Center, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J. Watson Research Center, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049413685","display_name":"Michael Gschwind","orcid":"https://orcid.org/0009-0001-4963-4915"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Gschwind","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM T. J. Watson Research Center, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J. Watson Research Center, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045722906","display_name":"Ruchir Puri","orcid":"https://orcid.org/0009-0006-8803-7079"},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ruchir Puri","raw_affiliation_strings":["IBM Thomas J. Watson Research Center, USA","IBM T. J. Watson Research Center, USA"],"affiliations":[{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, USA","institution_ids":["https://openalex.org/I4210114115"]},{"raw_affiliation_string":"IBM T. J. Watson Research Center, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5026584653"],"corresponding_institution_ids":["https://openalex.org/I4210114115"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.64933837,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"13","issue":null,"first_page":"179","last_page":"182"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9359920024871826},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7272021770477295},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.6484411358833313},{"id":"https://openalex.org/keywords/carry-save-adder","display_name":"Carry-save adder","score":0.5699650645256042},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5451757311820984},{"id":"https://openalex.org/keywords/dataflow","display_name":"Dataflow","score":0.5300096273422241},{"id":"https://openalex.org/keywords/prefix","display_name":"Prefix","score":0.50528484582901},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48646852374076843},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.46492671966552734},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4124067425727844},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4073660969734192},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33154869079589844},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13721346855163574},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11068418622016907},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.10409682989120483},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08459299802780151},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.07901632785797119}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9359920024871826},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7272021770477295},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.6484411358833313},{"id":"https://openalex.org/C3227080","wikidata":"https://www.wikidata.org/wiki/Q5046770","display_name":"Carry-save adder","level":4,"score":0.5699650645256042},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5451757311820984},{"id":"https://openalex.org/C96324660","wikidata":"https://www.wikidata.org/wiki/Q205446","display_name":"Dataflow","level":2,"score":0.5300096273422241},{"id":"https://openalex.org/C141603448","wikidata":"https://www.wikidata.org/wiki/Q134830","display_name":"Prefix","level":2,"score":0.50528484582901},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48646852374076843},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.46492671966552734},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4124067425727844},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4073660969734192},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33154869079589844},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13721346855163574},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11068418622016907},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.10409682989120483},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08459299802780151},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.07901632785797119},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2009.5280873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.46000000834465027,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W196500522","https://openalex.org/W1485581708","https://openalex.org/W1556050292","https://openalex.org/W1582324226","https://openalex.org/W1591490338","https://openalex.org/W1604826642","https://openalex.org/W1963965124","https://openalex.org/W1996212848","https://openalex.org/W2040628887","https://openalex.org/W2097414281","https://openalex.org/W2125322466","https://openalex.org/W2131647018","https://openalex.org/W2135874222","https://openalex.org/W2137589342","https://openalex.org/W2143462372","https://openalex.org/W2147847555","https://openalex.org/W2152473162","https://openalex.org/W2156359452","https://openalex.org/W2168543008","https://openalex.org/W4285719527","https://openalex.org/W6608091574","https://openalex.org/W6636304122","https://openalex.org/W6678742877"],"related_works":["https://openalex.org/W2489015823","https://openalex.org/W2516396101","https://openalex.org/W2186498568","https://openalex.org/W4295540194","https://openalex.org/W2129868416","https://openalex.org/W2015457513","https://openalex.org/W2364181090","https://openalex.org/W4255416339","https://openalex.org/W2112595260","https://openalex.org/W3082514006"],"abstract_inverted_index":{"64-bit":[0],"adders":[1],"of":[2,36],"various":[3],"prefix":[4,51],"algorithms":[5],"are":[6,53],"designed":[7],"using":[8],"a":[9,34],"novel":[10],"dataflow":[11],"synthesis":[12,15],"methodology.":[13],"Our":[14],"methodology":[16],"offers":[17],"robust":[18],"adder":[19,38,64],"solutions":[20],"typically":[21],"used":[22],"for":[23,33,59],"high-performance":[24,61],"microprocessor":[25],"needs.":[26],"We":[27],"have":[28],"analyzed":[29],"the":[30,45],"power-performance":[31],"tradeoffs":[32],"portfolio":[35],"popular":[37],"topologies":[39],"and":[40,62],"design":[41],"styles.":[42],"In":[43],"particular,":[44],"intrinsically":[46],"sparser":[47],"designs":[48],"in":[49],"hierarchical":[50],"scheme":[52],"demonstrated":[54],"to":[55],"be":[56],"preferable":[57],"choices":[58],"both":[60],"low-power":[63],"applications.":[65]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}