{"id":"https://openalex.org/W2149523154","doi":"https://doi.org/10.1109/cicc.2009.5280856","title":"A 12-b 56MS/s pipelined ADC in 65nm CMOS","display_name":"A 12-b 56MS/s pipelined ADC in 65nm CMOS","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2149523154","doi":"https://doi.org/10.1109/cicc.2009.5280856","mag":"2149523154"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2009.5280856","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280856","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063082947","display_name":"A. Leuciuc","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"A. Leuciuc","raw_affiliation_strings":["Cadence Design Systems, Columbia, MD, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Columbia, MD, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004933008","display_name":"William P. Evans","orcid":"https://orcid.org/0000-0002-5878-611X"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"W. Evans","raw_affiliation_strings":["Cadence Design Systems, Columbia, MD, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Columbia, MD, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5090737738","display_name":"Hongyu Ji","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Ji","raw_affiliation_strings":["Cadence Design Systems, Columbia, MD, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Columbia, MD, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033283908","display_name":"E. Naviasky","orcid":null},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E. Naviasky","raw_affiliation_strings":["Cadence Design Systems, Columbia, MD, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Columbia, MD, USA","institution_ids":["https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100618515","display_name":"Xiaoyong He","orcid":"https://orcid.org/0000-0002-7302-4578"},"institutions":[{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"X. He","raw_affiliation_strings":["Cadence Design Systems, Columbia, MD, USA"],"affiliations":[{"raw_affiliation_string":"Cadence Design Systems, Columbia, MD, USA","institution_ids":["https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5063082947"],"corresponding_institution_ids":["https://openalex.org/I66217453"],"apc_list":null,"apc_paid":null,"fwci":0.8894,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.76499675,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"267","last_page":"270"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7398526668548584},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6124411821365356},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.5818674564361572},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5302367210388184},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.5059296488761902},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.48463258147239685},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4743684232234955},{"id":"https://openalex.org/keywords/transient","display_name":"Transient (computer programming)","score":0.46972835063934326},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4535480737686157},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4362197518348694},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.40634724497795105},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3100981116294861},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19369280338287354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.11403629183769226},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.06923907995223999}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7398526668548584},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6124411821365356},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.5818674564361572},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5302367210388184},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.5059296488761902},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.48463258147239685},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4743684232234955},{"id":"https://openalex.org/C2780799671","wikidata":"https://www.wikidata.org/wiki/Q17087362","display_name":"Transient (computer programming)","level":2,"score":0.46972835063934326},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4535480737686157},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4362197518348694},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.40634724497795105},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3100981116294861},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19369280338287354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.11403629183769226},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.06923907995223999},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2009.5280856","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280856","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1976248159","https://openalex.org/W2068999327","https://openalex.org/W2073140918","https://openalex.org/W2077839561","https://openalex.org/W2081855094","https://openalex.org/W2101468035","https://openalex.org/W2124710623","https://openalex.org/W2132449418","https://openalex.org/W2138634253","https://openalex.org/W6667785019"],"related_works":["https://openalex.org/W2069427488","https://openalex.org/W4281694563","https://openalex.org/W2080696413","https://openalex.org/W1506140395","https://openalex.org/W2163182355","https://openalex.org/W4240158017","https://openalex.org/W2011204264","https://openalex.org/W2094356678","https://openalex.org/W2070694218","https://openalex.org/W2910817228"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,11,28],"1.2":[4],"V,":[5],"12-b":[6],"pipelined":[7],"ADC":[8],"implemented":[9],"in":[10,27,45],"65":[12],"nm":[13],"CMOS":[14],"process.":[15],"The":[16,53],"circuit":[17,54],"design":[18],"techniques":[19,57],"used":[20,39],"to":[21,40],"obtain":[22],"high":[23],"gain":[24],"operational":[25],"amplifiers":[26],"deep-submicron":[29],"process":[30],"are":[31],"described.":[32],"A":[33],"novel":[34],"top-level":[35],"simulation":[36],"methodology":[37],"is":[38],"quantify":[41],"the":[42],"transient":[43],"errors":[44],"each":[46],"subrange":[47],"stage,":[48],"allowing":[49],"their":[50],"optimal":[51],"design.":[52],"employs":[55],"various":[56],"for":[58],"power":[59],"reduction:":[60],"class":[61],"A-B":[62],"op-amps,":[63],"improved":[64],"reference":[65],"design,":[66],"and":[67],"frequency-to-current":[68],"biasing.":[69]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}