{"id":"https://openalex.org/W2293593262","doi":"https://doi.org/10.1109/cicc.2009.5280730","title":"Memory trends","display_name":"Memory trends","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2293593262","doi":"https://doi.org/10.1109/cicc.2009.5280730","mag":"2293593262"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2009.5280730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5016704219","display_name":"Vikas Chandra","orcid":"https://orcid.org/0009-0005-4996-8455"},"institutions":[{"id":"https://openalex.org/I2801109035","display_name":"ARM (United Kingdom)","ror":"https://ror.org/04mmhzs81","country_code":"GB","type":"company","lineage":["https://openalex.org/I2801109035"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Vikas Chandra","raw_affiliation_strings":["ARM, UK"],"affiliations":[{"raw_affiliation_string":"ARM, UK","institution_ids":["https://openalex.org/I2801109035"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5076614695","display_name":"T. Andr\u00e9","orcid":null},"institutions":[{"id":"https://openalex.org/I4210093483","display_name":"Everspin Technologies (United States)","ror":"https://ror.org/00hn06s81","country_code":"US","type":"company","lineage":["https://openalex.org/I4210093483"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tom Andre","raw_affiliation_strings":["Everspin Technologies, USA"],"affiliations":[{"raw_affiliation_string":"Everspin Technologies, USA","institution_ids":["https://openalex.org/I4210093483"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5016704219"],"corresponding_institution_ids":["https://openalex.org/I2801109035"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.20221895,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.8938000202178955,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.8938000202178955,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.8830000162124634,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.8008000254631042,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.7611662745475769},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7115091681480408},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6943140029907227},{"id":"https://openalex.org/keywords/variety","display_name":"Variety (cybernetics)","score":0.636018693447113},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5550888180732727},{"id":"https://openalex.org/keywords/universal-memory","display_name":"Universal memory","score":0.4984090328216553},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.47874563932418823},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4692171812057495},{"id":"https://openalex.org/keywords/dynamic-random-access-memory","display_name":"Dynamic random-access memory","score":0.4661829173564911},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.44961023330688477},{"id":"https://openalex.org/keywords/non-volatile-random-access-memory","display_name":"Non-volatile random-access memory","score":0.44123658537864685},{"id":"https://openalex.org/keywords/non-volatile-memory","display_name":"Non-volatile memory","score":0.4367034435272217},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4144648313522339},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.3230961859226227},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2522251605987549},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.24400871992111206},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.21999043226242065},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.16710010170936584},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09579691290855408}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.7611662745475769},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7115091681480408},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6943140029907227},{"id":"https://openalex.org/C136197465","wikidata":"https://www.wikidata.org/wiki/Q1729295","display_name":"Variety (cybernetics)","level":2,"score":0.636018693447113},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5550888180732727},{"id":"https://openalex.org/C195053848","wikidata":"https://www.wikidata.org/wiki/Q7894141","display_name":"Universal memory","level":5,"score":0.4984090328216553},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.47874563932418823},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4692171812057495},{"id":"https://openalex.org/C118702147","wikidata":"https://www.wikidata.org/wiki/Q189396","display_name":"Dynamic random-access memory","level":3,"score":0.4661829173564911},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.44961023330688477},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.44123658537864685},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.4367034435272217},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4144648313522339},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.3230961859226227},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2522251605987549},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.24400871992111206},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.21999043226242065},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.16710010170936584},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09579691290855408}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2009.5280730","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2009.5280730","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6100000143051147}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2094308961","https://openalex.org/W4386903460","https://openalex.org/W2268596372","https://openalex.org/W2990977884","https://openalex.org/W1030357071","https://openalex.org/W1572401189","https://openalex.org/W2065778483","https://openalex.org/W2544687927","https://openalex.org/W2186356227","https://openalex.org/W3011604854"],"abstract_inverted_index":{"A":[0],"wide":[1],"variety":[2],"of":[3],"memory":[4],"topics":[5],"addressing":[6],"design":[7],"trends":[8],"at":[9],"advanced":[10],"technology":[11],"nodes.":[12],"Variation":[13],"tolerant":[14],"and":[15,31],"low":[16],"power":[17],"approaches":[18],"are":[19],"discussed":[20],"as":[21,23],"well":[22],"their":[24],"application":[25],"to":[26],"SRAM,":[27],"DRAM,":[28],"Non-volatile":[29],"memories":[30],"DDR5":[32],"interfaces.":[33]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}