{"id":"https://openalex.org/W2160184383","doi":"https://doi.org/10.1109/cicc.2008.4672061","title":"RASP 2.8: A new generation of floating-gate based field programmable analog array","display_name":"RASP 2.8: A new generation of floating-gate based field programmable analog array","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2160184383","doi":"https://doi.org/10.1109/cicc.2008.4672061","mag":"2160184383"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2008.4672061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2008.4672061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5002380437","display_name":"Arindam Basu","orcid":"https://orcid.org/0000-0003-1035-8770"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Arindam Basu","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108508698","display_name":"Christopher M. Twigg","orcid":null},"institutions":[{"id":"https://openalex.org/I123946342","display_name":"Binghamton University","ror":"https://ror.org/008rmbt77","country_code":"US","type":"education","lineage":["https://openalex.org/I123946342"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Christopher M. Twigg","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Binghamton University, Binghamton, NY, USA","institution_ids":["https://openalex.org/I123946342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007273807","display_name":"Stephen Brink","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen Brink","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105781337","display_name":"P. Hasler","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Paul Hasler","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111494347","display_name":"Csaba Petre","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Csaba Petre","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103453478","display_name":"Shubha Ramakrishnan","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shubha Ramakrishnan","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5027034406","display_name":"Scott Koziol","orcid":"https://orcid.org/0000-0002-5510-294X"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Scott Koziol","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091068770","display_name":"Craig Schlottmann","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Craig Schlottmann","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5002380437"],"corresponding_institution_ids":["https://openalex.org/I130701444"],"apc_list":null,"apc_paid":null,"fwci":5.5711,"has_fulltext":false,"cited_by_count":30,"citation_normalized_percentile":{"value":0.96066699,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"49","issue":null,"first_page":"213","last_page":"216"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.8494345545768738},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.7624356150627136},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6217613816261292},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.5265940427780151},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5124778747558594},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.49630409479141235},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4778956174850464},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.44704511761665344},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.44384995102882385},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4417800307273865},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4364449381828308},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4221712350845337},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4112124741077423},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32520151138305664},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3210337162017822},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2599540650844574},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10624149441719055},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07490694522857666}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.8494345545768738},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.7624356150627136},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6217613816261292},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.5265940427780151},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5124778747558594},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.49630409479141235},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4778956174850464},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.44704511761665344},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.44384995102882385},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4417800307273865},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4364449381828308},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4221712350845337},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4112124741077423},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32520151138305664},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3210337162017822},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2599540650844574},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10624149441719055},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07490694522857666},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2008.4672061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2008.4672061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7699999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1992249483","https://openalex.org/W2046857741","https://openalex.org/W2100734450","https://openalex.org/W2112100629","https://openalex.org/W2168153801"],"related_works":["https://openalex.org/W2014165129","https://openalex.org/W2466591189","https://openalex.org/W2154814801","https://openalex.org/W2376859467","https://openalex.org/W1972395546","https://openalex.org/W2017736121","https://openalex.org/W2038293309","https://openalex.org/W3163714531","https://openalex.org/W4309935840","https://openalex.org/W2764789987"],"abstract_inverted_index":{"The":[0,43,101],"RASP":[1],"2.8":[2],"is":[3,104],"a":[4,20],"very":[5],"powerful":[6],"reconfigurable":[7],"analog":[8,14],"computing":[9],"platform":[10],"with":[11,127],"thirty-two":[12],"computational":[13],"blocks":[15,37],"(CABs).":[16],"Each":[17],"CAB":[18,51],"has":[19],"wide":[21,33],"variety":[22],"of":[23,69,85,88],"sub-circuits":[24],"ranging":[25],"in":[26,49,67],"granularity":[27],"from":[28],"multipliers":[29],"and":[30,40,46,94,98],"programmable":[31,44],"offset":[32],"linear":[34],"range":[35,81],"Gm":[36],"to":[38,107],"NMOS":[39],"PMOS":[41],"transistors.":[42,57],"interconnects":[45],"circuit":[47],"elements":[48],"the":[50,123],"are":[52,136],"implemented":[53],"using":[54],"floating":[55],"gate":[56],"This":[58],"system":[59,134],"exhibits":[60],"significant":[61],"performance":[62,118],"enhancements":[63],"over":[64],"its":[65],"predecessor":[66],"terms":[68],"achievable":[70],"signal":[71],"bandwidth":[72,103],"(>":[73,77,82,91],"50":[74],"MHz),":[75],"accuracy":[76],"9":[78],"bits),":[79],"dynamic":[80],"7":[83],"decades":[84],"current),":[86],"speed":[87],"floating-gate":[89],"programming":[90],"200":[92],"gates/sec)":[93],"isolation":[95],"between":[96],"ON":[97],"OFF":[99],"switches.":[100],"improved":[102,109,119],"primarily":[105],"due":[106],"an":[108,128],"routing":[110],"fabric":[111],"that":[112],"includes":[113],"nearest":[114],"neighbor":[115],"connections.":[116],"Programming":[117],"drastically":[120],"by":[121],"implementing":[122],"entire":[124],"algorithm":[125],"on-chip":[126],"SPI":[129],"digital":[130],"interface.":[131],"Several":[132],"complex":[133],"examples":[135],"presented.":[137]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
