{"id":"https://openalex.org/W2133262923","doi":"https://doi.org/10.1109/cicc.2008.4672010","title":"A 90–240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking","display_name":"A 90–240MHz hysteretic controlled DC-DC buck converter with digital PLL frequency locking","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2133262923","doi":"https://doi.org/10.1109/cicc.2008.4672010","mag":"2133262923"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2008.4672010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2008.4672010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100339777","display_name":"Pengfei Li","orcid":"https://orcid.org/0000-0003-1612-7711"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Pengfei Li","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074645582","display_name":"Deepak Bhatia","orcid":"https://orcid.org/0000-0001-7695-8483"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Deepak Bhatia","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101695982","display_name":"Xue Lin","orcid":"https://orcid.org/0000-0003-4971-1375"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lin Xue","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039467434","display_name":"Rizwan Bashirullah","orcid":null},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rizwan Bashirullah","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100339777"],"corresponding_institution_ids":["https://openalex.org/I33213144"],"apc_list":null,"apc_paid":null,"fwci":1.6955,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.84296646,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ripple","display_name":"Ripple","score":0.5906401872634888},{"id":"https://openalex.org/keywords/buck-converter","display_name":"Buck converter","score":0.5904515385627747},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5900296568870544},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5111146569252014},{"id":"https://openalex.org/keywords/digital-control","display_name":"Digital control","score":0.5038322806358337},{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.4799764156341553},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.47852623462677},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.47394871711730957},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4207053482532501},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.37838396430015564},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3657926917076111},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.30547940731048584},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2409878671169281},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.07871776819229126}],"concepts":[{"id":"https://openalex.org/C2779599953","wikidata":"https://www.wikidata.org/wiki/Q1776117","display_name":"Ripple","level":3,"score":0.5906401872634888},{"id":"https://openalex.org/C150818752","wikidata":"https://www.wikidata.org/wiki/Q83804","display_name":"Buck converter","level":3,"score":0.5904515385627747},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5900296568870544},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5111146569252014},{"id":"https://openalex.org/C158411068","wikidata":"https://www.wikidata.org/wiki/Q2720568","display_name":"Digital control","level":2,"score":0.5038322806358337},{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.4799764156341553},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.47852623462677},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.47394871711730957},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4207053482532501},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.37838396430015564},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3657926917076111},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.30547940731048584},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2409878671169281},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.07871776819229126},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2008.4672010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2008.4672010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1936892133","https://openalex.org/W1969650916","https://openalex.org/W2070061481","https://openalex.org/W2081436083","https://openalex.org/W2120542708","https://openalex.org/W2143000636","https://openalex.org/W2149594139","https://openalex.org/W6642736963","https://openalex.org/W6671010942"],"related_works":["https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2059960378","https://openalex.org/W2043945969","https://openalex.org/W2103754166","https://openalex.org/W2058003010","https://openalex.org/W1994059163","https://openalex.org/W2110868325","https://openalex.org/W3113661469"],"abstract_inverted_index":{"This":[0],"paper":[1],"reports":[2],"a":[3,28,52,62,79,105,112,118],"digital":[4,132],"phase":[5,83],"locked":[6,60],"loop":[7],"(DPLL)":[8],"frequency":[9,14,26,38,70],"locking":[10],"technique":[11,22],"for":[12,111],"high":[13],"hysteretic":[15,87],"controlled":[16],"dc-dc":[17],"buck":[18],"converters.":[19],"The":[20,47,95,125],"proposed":[21],"achieves":[23,97],"constant":[24],"operating":[25],"over":[27,51],"wide":[29,53],"output":[30,43,90],"voltage":[31,44],"range,":[32],"eliminating":[33],"the":[34,67],"dependence":[35],"of":[36,55,93,100,108],"switching":[37,69],"on":[39],"duty":[40],"cycle":[41],"or":[42],"conversion":[45,91],"range.":[46],"DPLL":[48],"is":[49],"programmable":[50],"range":[54,92],"parameters":[56],"and":[57,89,117],"can":[58],"be":[59],"to":[61,65],"reference":[63],"clock":[64],"ensure":[66],"converter":[68,84,96],"falls":[71],"outside":[72],"power":[73],"supply":[74],"resonance":[75],"bands.":[76],"We":[77],"demonstrate":[78],"90-240":[80],"MHz":[81],"single":[82],"with":[85],"fast":[86],"control":[88],"33%-80%.":[94],"an":[98],"efficiency":[99],"80%":[101],"at":[102],"180":[103],"MHz,":[104],"load":[106],"response":[107],"40":[109],"ns":[110],"120":[113],"mA":[114],"current":[115],"step":[116],"peak-to-peak":[119],"ripple":[120],"less":[121],"than":[122],"25":[123],"mV.":[124],"circuit":[126],"was":[127],"implemented":[128],"in":[129],"130":[130],"nm":[131],"CMOS":[133],"process.":[134]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}