{"id":"https://openalex.org/W2169808279","doi":"https://doi.org/10.1109/cicc.2007.4405728","title":"Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing","display_name":"Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing","publication_year":2007,"publication_date":"2007-09-01","ids":{"openalex":"https://openalex.org/W2169808279","doi":"https://doi.org/10.1109/cicc.2007.4405728","mag":"2169808279"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2007.4405728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2007.4405728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085791392","display_name":"Akihiro Nakamura","orcid":"https://orcid.org/0000-0001-7938-5254"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nakamura Akihiro","raw_affiliation_strings":["Department of VLSI System Design, Ritsumeikan University, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of VLSI System Design, Ritsumeikan University, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5097177615","display_name":"Masahide Kawaharazaki","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahide Kawaharazaki","raw_affiliation_strings":["Department of VLSI System Design, Ritsumeikan University, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of VLSI System Design, Ritsumeikan University, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102076246","display_name":"Masaya Yoshikawa","orcid":null},"institutions":[{"id":"https://openalex.org/I96636082","display_name":"Meijo University","ror":"https://ror.org/04h42fc75","country_code":"JP","type":"education","lineage":["https://openalex.org/I96636082"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masaya Yoshikawa","raw_affiliation_strings":["Department of Information Engineering, Meijo University, Aichi, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Information Engineering, Meijo University, Aichi, Japan","institution_ids":["https://openalex.org/I96636082"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007179822","display_name":"Takeshi Fujino","orcid":"https://orcid.org/0000-0001-9441-3137"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takeshi Fujino","raw_affiliation_strings":["Department of VLSI System Design, Ritsumeikan University, Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of VLSI System Design, Ritsumeikan University, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3741,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.67438501,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"261","last_page":"264"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9940000176429749,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9916999936103821,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9898999929428101,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/xnor-gate","display_name":"XNOR gate","score":0.8039905428886414},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6838400363922119},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.6819597482681274},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6464083194732666},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5894763469696045},{"id":"https://openalex.org/keywords/nand-logic","display_name":"NAND logic","score":0.5292272567749023},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.5106914639472961},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.5043505430221558},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.49936914443969727},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.48920297622680664},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4199489951133728},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.38208019733428955},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3532388210296631},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.348599910736084},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3366274833679199},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27483314275741577},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2570042312145233},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2564484775066376},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.17852848768234253},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08441030979156494}],"concepts":[{"id":"https://openalex.org/C57684291","wikidata":"https://www.wikidata.org/wiki/Q1336142","display_name":"XNOR gate","level":4,"score":0.8039905428886414},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6838400363922119},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.6819597482681274},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6464083194732666},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5894763469696045},{"id":"https://openalex.org/C7234692","wikidata":"https://www.wikidata.org/wiki/Q4116068","display_name":"NAND logic","level":4,"score":0.5292272567749023},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.5106914639472961},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.5043505430221558},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.49936914443969727},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.48920297622680664},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4199489951133728},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.38208019733428955},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3532388210296631},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.348599910736084},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3366274833679199},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27483314275741577},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2570042312145233},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2564484775066376},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.17852848768234253},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08441030979156494}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/cicc.2007.4405728","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2007.4405728","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.117.3456","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.117.3456","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ritsumei.ac.jp/se/re/fujinolab/thesis/cicc2007_nakamura_vpex.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education","score":0.7099999785423279}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1977850862","https://openalex.org/W1986978106","https://openalex.org/W1989882158","https://openalex.org/W2009196135","https://openalex.org/W2051743037","https://openalex.org/W2145262919","https://openalex.org/W2166135813","https://openalex.org/W2548743898","https://openalex.org/W4285719527","https://openalex.org/W6681441223"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W2014165129","https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W2466591189","https://openalex.org/W2764789987","https://openalex.org/W3022525969","https://openalex.org/W2054740893","https://openalex.org/W1904803855","https://openalex.org/W2169808279"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"the":[5,130,140],"novel":[6],"architecture":[7,134],"of":[8,35,38,94,110,117,125,132],"VCLD":[9],"(v\u0332ia":[10,16],"c\u0332onfigurable":[11],"l\u0332ogic":[12],"d\u0332evice)":[13],"called":[14],"VPEX":[15,36,111,133],"p\u0332rogrammable":[17],"logic":[18,32,60,93],"using":[19,89,104],"e\u0332x\u0332clusive-OR":[20],"array)":[21],"which":[22,56],"is":[23,112,139],"optimized":[24],"for":[25,143],"electron":[26],"beam":[27],"(EB)":[28],"direct":[29,137],"writing.":[30],"The":[31,49,92,107],"element":[33],"(LE)":[34],"consists":[37],"complex":[39],"gate":[40],"type":[41],"exclusive":[42],"OR":[43,65,69],"(EXOR)":[44],"and":[45,75,119,135],"inverter":[46],"(NOT)":[47],"gates.":[48],"single":[50],"LE":[51,96],"can":[52,85,97],"output":[53],"12":[54],"logics":[55],"include":[57],"all":[58],"2-inputs":[59],"functions":[61],"(NAND,":[62],"NOR":[63],"AND,":[64,67],"bubble":[66,68],"XOR":[70],"XNOR),":[71],"3":[72],"inputs":[73],"AOI21":[74],"inverted-output":[76],"multiplexer":[77],"(MUXI)":[78],"by":[79,88,100],"changing":[80],"via-1":[81],"layout.":[82],"Scan":[83],"D-FlipFlop":[84],"be":[86,98],"composed":[87],"5":[90],"LEs.":[91],"each":[95],"defined":[99],"double":[101],"EB":[102,136],"exposure":[103],"\"character":[105],"beam\".":[106],"speed":[108],"performance":[109],"much":[113],"better":[114],"than":[115,123],"that":[116,124,129],"FPGAs,":[118],"1.5":[120],"times":[121],"worse":[122],"ASICs.":[126],"We":[127],"believe":[128],"combination":[131],"writing":[138],"best":[141],"solution":[142],"low-volume":[144],"production":[145],"LSIs.":[146]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
