{"id":"https://openalex.org/W2129155426","doi":"https://doi.org/10.1109/cicc.2007.4405673","title":"A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology","display_name":"A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W2129155426","doi":"https://doi.org/10.1109/cicc.2007.4405673","mag":"2129155426"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2007.4405673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2007.4405673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055909346","display_name":"L. Wissel","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Larry Wissel","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071792287","display_name":"Harold Pilo","orcid":"https://orcid.org/0009-0002-6782-965X"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Harold Pilo","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109229312","display_name":"Chris LeBlanc","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chris LeBlanc","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100730228","display_name":"Xiaopeng Wang","orcid":"https://orcid.org/0000-0003-0384-9758"},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiaopeng Wang","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108799944","display_name":"Steve Lamphier","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steve Lamphier","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061083306","display_name":"Michael Fragano","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Michael Fragano","raw_affiliation_strings":["IBM Systems and Technology Group, Essex Junction, VT, USA","IBM, Essex"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IBM Systems and Technology Group, Essex Junction, VT, USA","institution_ids":[]},{"raw_affiliation_string":"IBM, Essex","institution_ids":["https://openalex.org/I1341412227"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1341412227"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"21","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7972528338432312},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.7213601469993591},{"id":"https://openalex.org/keywords/access-time","display_name":"Access time","score":0.6718550324440002},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6199520230293274},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.616473913192749},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5888833403587341},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5841178297996521},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5579121112823486},{"id":"https://openalex.org/keywords/column","display_name":"Column (typography)","score":0.54006028175354},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4696432948112488},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.44020533561706543},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4128465950489044},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.390740305185318},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3316945433616638},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32273542881011963},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2174684703350067},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20330902934074402},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.15330275893211365},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.13781797885894775},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12013724446296692}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7972528338432312},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.7213601469993591},{"id":"https://openalex.org/C194080101","wikidata":"https://www.wikidata.org/wiki/Q46306","display_name":"Access time","level":2,"score":0.6718550324440002},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6199520230293274},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.616473913192749},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5888833403587341},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5841178297996521},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5579121112823486},{"id":"https://openalex.org/C2780551164","wikidata":"https://www.wikidata.org/wiki/Q2306599","display_name":"Column (typography)","level":3,"score":0.54006028175354},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4696432948112488},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.44020533561706543},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4128465950489044},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.390740305185318},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3316945433616638},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32273542881011963},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2174684703350067},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20330902934074402},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.15330275893211365},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.13781797885894775},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12013724446296692},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2007.4405673","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2007.4405673","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 IEEE Custom Integrated Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5199999809265137}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1501207292","https://openalex.org/W1515034435","https://openalex.org/W1822414784","https://openalex.org/W2107008988","https://openalex.org/W4238507348","https://openalex.org/W6630014055","https://openalex.org/W6631090411"],"related_works":["https://openalex.org/W2136045454","https://openalex.org/W2074944429","https://openalex.org/W1991075467","https://openalex.org/W2389637992","https://openalex.org/W2609881373","https://openalex.org/W4387697157","https://openalex.org/W2172029144","https://openalex.org/W4363620538","https://openalex.org/W1504951709","https://openalex.org/W1970147343"],"abstract_inverted_index":{"A":[0],"fixed-configuration":[1,22],"custom":[2],"SRAM":[3,17,50],"macro":[4],"with":[5],"a":[6],"highly-scalable":[7],"architecture":[8],"was":[9],"used":[10,69],"as":[11],"the":[12,52,76],"basis":[13],"for":[14,70],"an":[15,42],"ASIC":[16],"compiler.":[18],"The":[19,48],"256":[20],"Kb":[21,62],"uses":[23],"dynamic":[24],"circuitry":[25,67],"(Pito":[26],"et":[27],"al.,":[28],"2004)":[29],"and":[30,34,56,78],"other":[31],"design":[32],"techniques,":[33],"has":[35],"been":[36],"demonstrated":[37],"in":[38,74],"silicon":[39],"to":[40,63],"have":[41],"access":[43],"time":[44],"of":[45],"550":[46],"ps.":[47],"compilable":[49],"extends":[51],"column":[53,79],"mux":[54],"options,":[55],"can":[57],"be":[58],"compiled":[59],"from":[60],"2":[61],"1.1":[64],"Mb.":[65],"Novel":[66],"is":[68],"efficient":[71],"redundancy":[72],"implementation":[73],"both":[75],"row":[77],"dimensions.":[80]},"counts_by_year":[{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
