{"id":"https://openalex.org/W2099320289","doi":"https://doi.org/10.1109/cicc.2005.1568738","title":"Challenge: variability characterization and modeling for 65- to 90-nm processes","display_name":"Challenge: variability characterization and modeling for 65- to 90-nm processes","publication_year":2006,"publication_date":"2006-01-18","ids":{"openalex":"https://openalex.org/W2099320289","doi":"https://doi.org/10.1109/cicc.2005.1568738","mag":"2099320289"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2005.1568738","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568738","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066616733","display_name":"H. Masuda","orcid":"https://orcid.org/0000-0002-5553-9201"},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"H. Masuda","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108507778","display_name":"S. Ohkawa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S.-i. Ohkawa","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108583073","display_name":"A. Kurokawa","orcid":null},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"A. Kurokawa","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087707920","display_name":"Masakazu Aoki","orcid":"https://orcid.org/0000-0003-1951-8400"},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Aoki","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Yokohama, Japan"],"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Yokohama, Japan","institution_ids":["https://openalex.org/I4210125918"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5066616733"],"corresponding_institution_ids":["https://openalex.org/I4210125918"],"apc_list":null,"apc_paid":null,"fwci":22.2108,"has_fulltext":false,"cited_by_count":150,"citation_normalized_percentile":{"value":0.99706147,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":"588","last_page":"595"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7925961017608643},{"id":"https://openalex.org/keywords/randomness","display_name":"Randomness","score":0.6843019127845764},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.6069974899291992},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5626944899559021},{"id":"https://openalex.org/keywords/variation","display_name":"Variation (astronomy)","score":0.5520409345626831},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5477322340011597},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5474893450737},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5263926982879639},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.523097038269043},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5043278932571411},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4624059498310089},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.4508891701698303},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.42539867758750916},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.42101311683654785},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2502066493034363},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22399774193763733},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.1914408802986145},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.10613301396369934},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09319919347763062},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09047049283981323}],"concepts":[{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7925961017608643},{"id":"https://openalex.org/C125112378","wikidata":"https://www.wikidata.org/wiki/Q176640","display_name":"Randomness","level":2,"score":0.6843019127845764},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.6069974899291992},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5626944899559021},{"id":"https://openalex.org/C2778334786","wikidata":"https://www.wikidata.org/wiki/Q1586270","display_name":"Variation (astronomy)","level":2,"score":0.5520409345626831},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5477322340011597},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5474893450737},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5263926982879639},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.523097038269043},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5043278932571411},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4624059498310089},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.4508891701698303},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.42539867758750916},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.42101311683654785},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2502066493034363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22399774193763733},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.1914408802986145},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.10613301396369934},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09319919347763062},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09047049283981323},{"id":"https://openalex.org/C44870925","wikidata":"https://www.wikidata.org/wiki/Q37547","display_name":"Astrophysics","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2005.1568738","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568738","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W43268415","https://openalex.org/W2057684575","https://openalex.org/W2080802281","https://openalex.org/W2099744220","https://openalex.org/W2106605025","https://openalex.org/W2116677528","https://openalex.org/W2118567051","https://openalex.org/W2126811283","https://openalex.org/W2140823559","https://openalex.org/W2167232152","https://openalex.org/W4237696035"],"related_works":["https://openalex.org/W2165367082","https://openalex.org/W2132668926","https://openalex.org/W2070693700","https://openalex.org/W3047211184","https://openalex.org/W3214737056","https://openalex.org/W4295186528","https://openalex.org/W3200538824","https://openalex.org/W1561071093","https://openalex.org/W1977643363","https://openalex.org/W2126835888"],"abstract_inverted_index":{"In":[0,35],"sub-100-nm":[1],"processes,":[2,14],"many":[3],"physical":[4,29],"phenomena":[5],"have":[6,57],"become":[7],"critical":[8],"issues":[9],"in":[10,22,49,102,120],"the":[11,50,65,80,85,103],"development":[12],"of":[13,28,68,79,89],"devices,":[15],"and":[16,75,123],"circuits.":[17],"To":[18],"achieve":[19],"reasonable":[20],"compromise":[21],"ASIC":[23],"design,":[24],"device-and":[25],"process-level":[26],"characterization":[27],"designs":[30],"is":[31],"a":[32,59,93],"fundamental":[33],"requirement.":[34],"this":[36],"paper,":[37],"we":[38],"address":[39],"topics":[40],"regarding":[41],"\"design":[42],"for":[43],"variability\",":[44],"which":[45,97],"are":[46],"increasingly":[47],"important":[48],"65-":[51],"to":[52,62,99,116],"90-nm":[53],"technology":[54],"era.":[55],"We":[56,108],"developed":[58],"new":[60],"test-structure":[61],"precisely":[63],"measure":[64],"on-chip":[66],"variation":[67,88,101,111],"key":[69],"LSI":[70],"components":[71],"(MOST,":[72],"R,":[73],"C,":[74],"circuit-delay).":[76],"Statistical":[77],"analysis":[78],"experimental":[81],"results":[82],"revealed":[83],"that":[84,110],"3/spl":[86],"sigma/":[87],"MOS":[90],"drive-current":[91],"within":[92],"chip":[94],"was":[95],"30%,":[96],"led":[98],"equal":[100],"circuit":[104],"propagation":[105],"delay":[106],"(Tpd).":[107],"found":[109],"can":[112],"be":[113],"suppressed":[114],"due":[115],"its":[117],"randomness":[118],"features":[119],"multi-stage":[121],"circuitry":[122],"high-performance,":[124],"large-gate-area":[125],"driver":[126],"CMOS":[127],"devices.":[128]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":2},{"year":2018,"cited_by_count":4},{"year":2016,"cited_by_count":6},{"year":2015,"cited_by_count":6},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":7},{"year":2012,"cited_by_count":13}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}