{"id":"https://openalex.org/W2111894524","doi":"https://doi.org/10.1109/cicc.2005.1568724","title":"Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application","display_name":"Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application","publication_year":2006,"publication_date":"2006-01-18","ids":{"openalex":"https://openalex.org/W2111894524","doi":"https://doi.org/10.1109/cicc.2005.1568724","mag":"2111894524"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2005.1568724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047060185","display_name":"Nam-Seog Kim","orcid":"https://orcid.org/0000-0002-1039-5945"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Nam-Seog Kim","raw_affiliation_strings":["SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","Memory Div., Samsung .Electron., Hwasung, South Korea"],"affiliations":[{"raw_affiliation_string":"SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Memory Div., Samsung .Electron., Hwasung, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110232432","display_name":"Uk-Rae Cho","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Uk-Rae Cho","raw_affiliation_strings":["SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","Memory Div., Samsung .Electron., Hwasung, South Korea"],"affiliations":[{"raw_affiliation_string":"SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Memory Div., Samsung .Electron., Hwasung, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5077048613","display_name":"Hyun-Geun Byun","orcid":null},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Hyun-Geun Byun","raw_affiliation_strings":["SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","Memory Div., Samsung .Electron., Hwasung, South Korea"],"affiliations":[{"raw_affiliation_string":"SRAM Design, Memory Division, Samsung Electronics Company Limited, Hwasung, Gyeonggi, South Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"Memory Div., Samsung .Electron., Hwasung, South Korea","institution_ids":["https://openalex.org/I2250650973"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5047060185"],"corresponding_institution_ids":["https://openalex.org/I2250650973"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.15538415,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"528","last_page":"531"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7386395931243896},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.6726398468017578},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5884715914726257},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49799203872680664},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.45167556405067444},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4434690773487091},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.43465346097946167},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4203700125217438},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4145064949989319},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2776080071926117},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.26374882459640503},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.25030046701431274},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19915571808815002}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7386395931243896},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.6726398468017578},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5884715914726257},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49799203872680664},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.45167556405067444},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4434690773487091},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.43465346097946167},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4203700125217438},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4145064949989319},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2776080071926117},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.26374882459640503},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.25030046701431274},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19915571808815002}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2005.1568724","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568724","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.800000011920929,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2124390946"],"related_works":["https://openalex.org/W2169622190","https://openalex.org/W2224788396","https://openalex.org/W2171851068","https://openalex.org/W2117541676","https://openalex.org/W2141594064","https://openalex.org/W2143420037","https://openalex.org/W1574257586","https://openalex.org/W849640194","https://openalex.org/W1506950392","https://openalex.org/W2496244846"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposed":[2,30,96],"DLL-based":[3],"quad":[4,16,35],"phase":[5,17,36,70,82],"core":[6],"clock":[7],"generator,":[8],"whose":[9],"operation":[10],"voltage":[11],"is":[12,67,75],"sub":[13],"1V.":[14],"The":[15,29,69,95],"clocks":[18,37],"are":[19],"used":[20],"to":[21],"transmit":[22],"DDR":[23],"data":[24],"and":[25,42,84],"complementary":[26],"echo":[27],"clocks.":[28],"DLL":[31],"generates":[32],"evenly":[33],"spaced":[34],"without":[38],"additional":[39],"delay":[40],"elements":[41],"duty":[43,53],"cycle":[44,54],"corrector,":[45],"so":[46],"it":[47],"has":[48],"no":[49],"systematic":[50],"error":[51,72],"from":[52],"correction.":[55],"To":[56],"reduce":[57],"the":[58],"amount":[59],"of":[60,73,79],"bang-bang":[61],"jitter,":[62],"a":[63],"new":[64],"interpolation":[65],"scheme":[66],"proposed.":[68],"shift":[71],"interpolator":[74],"less":[76],"than":[77],"2%":[78],"ideal":[80],"one":[81],"step":[83],"doesn't":[85],"have":[86],"3-code":[87],"dither":[88],"at":[89,91],"lock":[90],"digitally":[92],"controlled":[93],"DLL.":[94],"circuits":[97],"were":[98],"fabricated":[99],"with":[100],"0.1":[101],"/spl":[102],"mu/m":[103],"CMOS":[104],"process.":[105]},"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":6},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
