{"id":"https://openalex.org/W2160955145","doi":"https://doi.org/10.1109/cicc.2005.1568650","title":"Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor","display_name":"Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor","publication_year":2006,"publication_date":"2006-01-18","ids":{"openalex":"https://openalex.org/W2160955145","doi":"https://doi.org/10.1109/cicc.2005.1568650","mag":"2160955145"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2005.1568650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5025164269","display_name":"T. Beacom","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"T. Beacom","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076902759","display_name":"T.C. Buchholtz","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"T. Buchholtz","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034597781","display_name":"Daryl Bradley","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Bradley","raw_affiliation_strings":["System and Technology Group, IBM Austin Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"System and Technology Group, IBM Austin Research Laboratory, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109994735","display_name":"J. E. Randolph","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Randolph","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079867709","display_name":"S.N. Storino","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Storino","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020197611","display_name":"M. Veldhuizen","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Veldhuizen","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036117786","display_name":"S.M. Dance","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Dance","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013787120","display_name":"J.B. Kuang","orcid":"https://orcid.org/0000-0003-2190-321X"},"institutions":[{"id":"https://openalex.org/I4210156936","display_name":"IBM Research - Austin","ror":"https://ror.org/05gjbbg60","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115","https://openalex.org/I4210156936"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J.B. Kuang","raw_affiliation_strings":["Research Division, Austin Research Laboratory, IBM Austin Research Laboratory, USA"],"affiliations":[{"raw_affiliation_string":"Research Division, Austin Research Laboratory, IBM Austin Research Laboratory, USA","institution_ids":["https://openalex.org/I4210156936"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020881477","display_name":"Stephen J. Schwinn","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Schwinn","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069625239","display_name":"S. Cox","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"S. Cox","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087418661","display_name":"F. Ziegler","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Ziegler","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008599998","display_name":"J. Kao","orcid":"https://orcid.org/0000-0003-2082-6937"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Kao","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003807673","display_name":"C.T. Li","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"C.T. Li","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022786469","display_name":"C. Tretz","orcid":null},"institutions":[{"id":"https://openalex.org/I1341412227","display_name":"IBM (United States)","ror":"https://ror.org/05hh8d621","country_code":"US","type":"company","lineage":["https://openalex.org/I1341412227"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C. Tretz","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM San Jose, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM San Jose, USA","institution_ids":["https://openalex.org/I1341412227"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061803148","display_name":"J. Cabellon","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Cabellon","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022801316","display_name":"A. Freemyer","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. Freemyer","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008678448","display_name":"M. Tubbs","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"M. Tubbs","raw_affiliation_strings":["Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA"],"affiliations":[{"raw_affiliation_string":"Engineering and Technology Services Systems and Technology Group, IBM Rochester, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":17,"corresponding_author_ids":["https://openalex.org/A5025164269"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17847686,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"232","last_page":"235"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9962999820709229,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6523173451423645},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.5633535385131836},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5302426815032959},{"id":"https://openalex.org/keywords/scalar","display_name":"Scalar (mathematics)","score":0.5155736804008484},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.47988927364349365},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42267847061157227},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.4222591817378998},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4183439016342163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3825094699859619},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37954211235046387},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3475803732872009},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21175900101661682},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.13401827216148376},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12172764539718628},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08700117468833923}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6523173451423645},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.5633535385131836},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5302426815032959},{"id":"https://openalex.org/C57691317","wikidata":"https://www.wikidata.org/wiki/Q1289248","display_name":"Scalar (mathematics)","level":2,"score":0.5155736804008484},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.47988927364349365},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42267847061157227},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.4222591817378998},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4183439016342163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3825094699859619},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37954211235046387},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3475803732872009},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21175900101661682},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.13401827216148376},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12172764539718628},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08700117468833923},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2005.1568650","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2005.1568650","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8399999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1571544561","https://openalex.org/W1575732703","https://openalex.org/W1582510115","https://openalex.org/W2135874222","https://openalex.org/W4285719527","https://openalex.org/W6634354345"],"related_works":["https://openalex.org/W2033778626","https://openalex.org/W2026780467","https://openalex.org/W2187110187","https://openalex.org/W2018697868","https://openalex.org/W2792315845","https://openalex.org/W2002371119","https://openalex.org/W4390492895","https://openalex.org/W2886225742","https://openalex.org/W4323662771","https://openalex.org/W2115579119"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,8,14],"design":[4],"and":[5,21,31,46,58,70],"implementation":[6],"of":[7,35,74],"vector":[9,22],"scalar":[10],"unit":[11],"(VSU)":[12],"in":[13,39],"first-generation":[15],"CELL":[16],"processor.":[17],"VSU":[18,26],"executes":[19],"floating-point":[20],"media":[23],"extension":[24],"instructions.":[25],"contains":[27],"1.7":[28],"million":[29],"transistors":[30],"occupies":[32],"an":[33],"area":[34,57],"3.1":[36],"mm/sup":[37],"2/":[38],"a":[40,71],"90nm":[41],"PD-SOI":[42],"technology.":[43],"Extensive":[44],"static":[45],"dynamic":[47],"circuit":[48],"techniques":[49],"are":[50],"used":[51],"to":[52],"optimize":[53],"performance":[54],"while":[55],"minimizing":[56],"power":[59],"simultaneously.":[60],"Full":[61],"functionality":[62],"is":[63],"observed":[64],"at":[65],"4.76":[66],"GHz,":[67],"1.3V":[68],"supply":[69],"chip":[72],"temperature":[73],"68/spl":[75],"deg/C.":[76]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}