{"id":"https://openalex.org/W2111046828","doi":"https://doi.org/10.1109/cicc.2004.1358904","title":"A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver","display_name":"A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver","publication_year":2004,"publication_date":"2004-11-30","ids":{"openalex":"https://openalex.org/W2111046828","doi":"https://doi.org/10.1109/cicc.2004.1358904","mag":"2111046828"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2004.1358904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007075394","display_name":"S.L.J. Gierkink","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"S.L.J. Gierkink","raw_affiliation_strings":["Agere Systems, Allentown, PA, USA"],"affiliations":[{"raw_affiliation_string":"Agere Systems, Allentown, PA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072189351","display_name":"D. Li","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Li","raw_affiliation_strings":["Agere Systems, Allentown, PA, USA","Intel Corporation, San Diego, CA, USA"],"affiliations":[{"raw_affiliation_string":"Agere Systems, Allentown, PA, USA","institution_ids":[]},{"raw_affiliation_string":"Intel Corporation, San Diego, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034108283","display_name":"R.C. Frye","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"R.C. Frye","raw_affiliation_strings":["Agere Systems, Allentown, PA, USA"],"affiliations":[{"raw_affiliation_string":"Agere Systems, Allentown, PA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075282759","display_name":"V. Boccuzzi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V. Boccuzzi","raw_affiliation_strings":["Agere Systems, Allentown, PA, USA"],"affiliations":[{"raw_affiliation_string":"Agere Systems, Allentown, PA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5007075394"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3292,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.64444233,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"629","last_page":"632"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.8394860029220581},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.822932243347168},{"id":"https://openalex.org/keywords/dbc","display_name":"dBc","score":0.7444767355918884},{"id":"https://openalex.org/keywords/transceiver","display_name":"Transceiver","score":0.7227041721343994},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.6200859546661377},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.5685757994651794},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.5665797591209412},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4991037845611572},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.485821008682251},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48119813203811646},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.47950464487075806},{"id":"https://openalex.org/keywords/dual-loop","display_name":"Dual loop","score":0.4180302023887634},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.41697099804878235},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4161984622478485},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3363253176212311},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.33194804191589355},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.2626556158065796},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2437598705291748},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.17891594767570496},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15280607342720032},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10710415244102478}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.8394860029220581},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.822932243347168},{"id":"https://openalex.org/C193523891","wikidata":"https://www.wikidata.org/wiki/Q1771950","display_name":"dBc","level":3,"score":0.7444767355918884},{"id":"https://openalex.org/C7720470","wikidata":"https://www.wikidata.org/wiki/Q954187","display_name":"Transceiver","level":3,"score":0.7227041721343994},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.6200859546661377},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.5685757994651794},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.5665797591209412},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4991037845611572},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.485821008682251},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48119813203811646},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.47950464487075806},{"id":"https://openalex.org/C2779691726","wikidata":"https://www.wikidata.org/wiki/Q5310214","display_name":"Dual loop","level":3,"score":0.4180302023887634},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.41697099804878235},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4161984622478485},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3363253176212311},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.33194804191589355},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.2626556158065796},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2437598705291748},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.17891594767570496},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15280607342720032},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10710415244102478},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2004.1358904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8600000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2144429677","https://openalex.org/W2519512094"],"related_works":["https://openalex.org/W4385624389","https://openalex.org/W2369807905","https://openalex.org/W4381745543","https://openalex.org/W1504159650","https://openalex.org/W4285329887","https://openalex.org/W2087564251","https://openalex.org/W2752021769","https://openalex.org/W2115565809","https://openalex.org/W2558244976","https://openalex.org/W2962482970"],"abstract_inverted_index":{"A":[0,58],"PLL-technique":[1],"is":[2,82],"introduced":[3],"to":[4,36],"enable":[5],"fast":[6],"switching":[7],"of":[8],"an":[9],"802.11":[10],"transceiver":[11],"local":[12],"oscillator":[13],"(LO)":[14],"between":[15],"a":[16,18,65],"low-and":[17],"zero":[19],"intermediate":[20],"frequency":[21],"(LIF/ZIF).":[22],"It":[23],"uses":[24],"dual":[25],"phase/frequency":[26],"detectors":[27],"(PFD),":[28],"charge":[29],"pumps":[30],"(CP)":[31],"and":[32],"on-chip":[33],"loop":[34,55],"filters":[35],"control":[37],"two":[38],"separate":[39],"low-leakage":[40],"VCO":[41],"tune":[42],"ports.":[43],"Each":[44],"PFD/tune":[45],"port":[46],"combination":[47],"can":[48],"be":[49],"(de)activated":[50],"separately,":[51],"without":[52],"disturbing":[53],"the":[54],"filter":[56],"charge.":[57],"50":[59],"kHz":[60,72],"bandwidth":[61],"integer-N":[62],"PLL":[63],"achieves":[64],"measured":[66,79],"7":[67],"MHz-jump":[68],"with":[69],"/spl":[70,76],"plusmn/20":[71],"accuracy":[73],"within":[74],"60":[75],"mu/s.":[77],"The":[78],"phase":[80],"noise":[81],"-123":[83],"dBc/Hz":[84],"at":[85],"1":[86],"MHz":[87],"offset.":[88]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}