{"id":"https://openalex.org/W2142033931","doi":"https://doi.org/10.1109/cicc.2004.1358846","title":"MAX II: A low-cost, high-performance LUT-based CPLD","display_name":"MAX II: A low-cost, high-performance LUT-based CPLD","publication_year":2004,"publication_date":"2004-11-30","ids":{"openalex":"https://openalex.org/W2142033931","doi":"https://doi.org/10.1109/cicc.2004.1358846","mag":"2142033931"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2004.1358846","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358846","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036033566","display_name":"Paul Leventis","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]},{"id":"https://openalex.org/I4210150916","display_name":"Alterra Power (Canada)","ror":"https://ror.org/04kzfav20","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210150916"]}],"countries":["CA","US"],"is_corresponding":true,"raw_author_name":"P. Leventis","raw_affiliation_strings":["Altera Corporation, Toronto, ONT, Canada","[Altera Corp., San Jose, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I4210150916"]},{"raw_affiliation_string":"[Altera Corp., San Jose, CA, USA]","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015241349","display_name":"B. Vest","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Vest","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA","[Altera Corp., San Jose, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]},{"raw_affiliation_string":"[Altera Corp., San Jose, CA, USA]","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038450823","display_name":"Mike Hutton","orcid":"https://orcid.org/0009-0009-0139-7242"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M. Hutton","raw_affiliation_strings":["Altera Corporation, San Jose, CA, USA","[Altera Corp., San Jose, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, San Jose, CA, USA","institution_ids":["https://openalex.org/I22433950"]},{"raw_affiliation_string":"[Altera Corp., San Jose, CA, USA]","institution_ids":["https://openalex.org/I22433950"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102968798","display_name":"David Lewis","orcid":"https://orcid.org/0000-0002-8126-5662"},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]},{"id":"https://openalex.org/I4210150916","display_name":"Alterra Power (Canada)","ror":"https://ror.org/04kzfav20","country_code":"CA","type":"company","lineage":["https://openalex.org/I4210150916"]}],"countries":["CA","US"],"is_corresponding":false,"raw_author_name":"D. Lewis","raw_affiliation_strings":["Altera Corporation, Toronto, ONT, Canada","[Altera Corp., San Jose, CA, USA]"],"affiliations":[{"raw_affiliation_string":"Altera Corporation, Toronto, ONT, Canada","institution_ids":["https://openalex.org/I4210150916"]},{"raw_affiliation_string":"[Altera Corp., San Jose, CA, USA]","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5036033566"],"corresponding_institution_ids":["https://openalex.org/I22433950","https://openalex.org/I4210150916"],"apc_list":null,"apc_paid":null,"fwci":0.5266,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.67610596,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"443","last_page":"446"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.9355859756469727},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.6018867492675781},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6007339954376221},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5978465676307678},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.5940883755683899},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5333727598190308},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5227803587913513},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5089714527130127},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.484925776720047},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43833011388778687},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.43627631664276123},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39990341663360596},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3267844319343567},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14881384372711182},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.08193773031234741}],"concepts":[{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.9355859756469727},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.6018867492675781},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6007339954376221},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5978465676307678},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.5940883755683899},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5333727598190308},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5227803587913513},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5089714527130127},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.484925776720047},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43833011388778687},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.43627631664276123},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39990341663360596},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3267844319343567},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14881384372711182},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.08193773031234741},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2004.1358846","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358846","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1597088765","https://openalex.org/W2007049691","https://openalex.org/W2038318386"],"related_works":["https://openalex.org/W1904803855","https://openalex.org/W3013792460","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W2990957507","https://openalex.org/W2374125170","https://openalex.org/W2360552902","https://openalex.org/W2584013459","https://openalex.org/W2047993371","https://openalex.org/W4379115868"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"the":[3,61,67],"MAX":[4,68],"II":[5],"CPLD":[6,11],"architecture.":[7],"Departing":[8],"from":[9],"traditional":[10],"product-term":[12],"logic":[13,47],"elements":[14],"and":[15,24,34,42,53],"global":[16],"routing,":[17],"it":[18],"instead":[19],"employs":[20],"FPGA-like":[21],"look-up":[22],"tables":[23],"channel-based":[25],"routing.":[26],"It":[27],"integrates":[28],"a":[29,35],"flash":[30],"memory":[31],"for":[32,38],"configuration":[33],"voltage":[36],"regulator":[37],"core":[39],"power":[40,58],"flexibility,":[41],"delivers":[43],"2.9/spl":[44],"times/":[45,50,56],"higher":[46],"density,":[48],"2.2/spl":[49],"greater":[51],"performance,":[52],"consumes":[54],">15/spl":[55],"less":[57],"in":[59],"1/6":[60],"die":[62],"size":[63],"of":[64],"its":[65],"predecessor,":[66],"7000A.":[69]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}