{"id":"https://openalex.org/W1555665998","doi":"https://doi.org/10.1109/cicc.2004.1358841","title":"Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay","display_name":"Hybrid approach to structured ASICs for minimizing the impact of reticle costs and interconnect delay","publication_year":2004,"publication_date":"2004-11-30","ids":{"openalex":"https://openalex.org/W1555665998","doi":"https://doi.org/10.1109/cicc.2004.1358841","mag":"1555665998"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2004.1358841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057277588","display_name":"John Allen Brown","orcid":null},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"J. Brown","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039492275","display_name":"R. Packer","orcid":null},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Packer","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061429300","display_name":"Jagdish Prasad","orcid":"https://orcid.org/0000-0002-2823-7013"},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Prasad","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071985936","display_name":"K. Kofford","orcid":null},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Kofford","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026035484","display_name":"T. Dye","orcid":null},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Dye","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5003557355","display_name":"Benjamin H. Kirk","orcid":"https://orcid.org/0000-0003-1964-0908"},"institutions":[{"id":"https://openalex.org/I100625452","display_name":"ON Semiconductor (United States)","ror":"https://ror.org/03nw6pt28","country_code":"US","type":"company","lineage":["https://openalex.org/I100625452"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B. Kirk","raw_affiliation_strings":["AMI Semiconductors, Inc., Pocatello, ID, USA","AMI Semicond., Inc., Pocatello, ID, USA"],"affiliations":[{"raw_affiliation_string":"AMI Semiconductors, Inc., Pocatello, ID, USA","institution_ids":["https://openalex.org/I100625452"]},{"raw_affiliation_string":"AMI Semicond., Inc., Pocatello, ID, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5057277588"],"corresponding_institution_ids":["https://openalex.org/I100625452"],"apc_list":null,"apc_paid":null,"fwci":0.6583,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.69092934,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"427","last_page":"429"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/reticle","display_name":"Reticle","score":0.9459037780761719},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6837767362594604},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6609598994255066},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6331726312637329},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5445889830589294},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.4876593351364136},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4557594060897827},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4546757638454437},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44446682929992676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4441227912902832},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.42713022232055664},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41500788927078247},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.324639230966568},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.23660752177238464},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20731142163276672},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.16777172684669495},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1612638533115387},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1372200846672058}],"concepts":[{"id":"https://openalex.org/C146617872","wikidata":"https://www.wikidata.org/wiki/Q1391868","display_name":"Reticle","level":3,"score":0.9459037780761719},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6837767362594604},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6609598994255066},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6331726312637329},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5445889830589294},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.4876593351364136},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4557594060897827},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4546757638454437},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44446682929992676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4441227912902832},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.42713022232055664},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41500788927078247},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.324639230966568},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.23660752177238464},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20731142163276672},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.16777172684669495},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1612638533115387},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1372200846672058},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2004.1358841","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358841","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W3200538824","https://openalex.org/W1977643363","https://openalex.org/W2070693700","https://openalex.org/W1561071093","https://openalex.org/W2097839191","https://openalex.org/W2902230348","https://openalex.org/W1975805813","https://openalex.org/W1501340521","https://openalex.org/W2069543777","https://openalex.org/W2028269328"],"abstract_inverted_index":{"System":[0],"designers":[1],"face":[2],"an":[3,36],"ever":[4],"more":[5,28],"complex":[6],"set":[7],"of":[8,60,76],"tradeoffs":[9],"in":[10],"developing":[11],"advanced":[12],"digital":[13],"systems.":[14],"Transistors":[15],"are":[16,26,33,94],"getting":[17,21,27],"faster,":[18],"interconnect":[19,62,79],"is":[20],"slower,":[22],"signal":[23],"integrity":[24],"issues":[25,63],"complex,":[29],"and":[30,57,84,119],"reticle":[31,55],"costs":[32,56],"exploding":[34],"at":[35,44],"exponential":[37],"rate.":[38],"This":[39],"paper":[40],"takes":[41],"a":[42,45,101],"look":[43],"unique":[46],"hybrid":[47],"processing":[48],"approach":[49],"for":[50],"structured":[51,98],"ASICs":[52,99],"which":[53],"reduces":[54],"avoids":[58],"many":[59],"the":[61,74],"associated":[64],"with":[65],"ultra-deep":[66],"sub-micron":[67],"(UDSM)":[68],"processes.":[69],"In":[70],"particular":[71],"it":[72],"investigates":[73],"impact":[75],"reduced":[77],"programmable":[78],"levels":[80],"on":[81],"routing":[82],"congestion":[83],"performance":[85],"relative":[86],"to":[87,96,100],"comparable":[88],"cell-based":[89],"ASIC":[90],"technologies.":[91],"Two":[92],"designs":[93],"used":[95],"compare":[97],"180nm":[102],"standard":[103],"cell":[104],"technology.":[105],"The":[106],"comparison":[107],"metrics":[108],"include":[109],"maximum":[110],"clock":[111,115,117],"rate,":[112],"density,":[113],"area,":[114],"latency,":[116],"skew":[118],"CT":[120],"fan":[121],"out.":[122]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}