{"id":"https://openalex.org/W2156380033","doi":"https://doi.org/10.1109/cicc.2004.1358839","title":"Platform IC with embedded via programmable logic for fast customization","display_name":"Platform IC with embedded via programmable logic for fast customization","publication_year":2004,"publication_date":"2004-11-30","ids":{"openalex":"https://openalex.org/W2156380033","doi":"https://doi.org/10.1109/cicc.2004.1358839","mag":"2156380033"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2004.1358839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042947591","display_name":"L. Cal\u00ec","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"L. Cali","raw_affiliation_strings":["Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057600694","display_name":"F. Lertora","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Lertora","raw_affiliation_strings":["Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023389485","display_name":"C. Gazzina","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"C. Gazzina","raw_affiliation_strings":["Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001727252","display_name":"M. Besana","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Besana","raw_affiliation_strings":["Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033815891","display_name":"M. Borgatti","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Borgatti","raw_affiliation_strings":["Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative System Design, NVM-DP, Central Research and Development, STMicroelectronics, Agrate-Brianza, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5042947591"],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":1.3165,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.80895211,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"85","issue":null,"first_page":"419","last_page":"422"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.7958709001541138},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.6734318733215332},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6689047813415527},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.6622945070266724},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6489227414131165},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.6118266582489014},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5963686108589172},{"id":"https://openalex.org/keywords/personalization","display_name":"Personalization","score":0.5713543891906738},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5435729622840881},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5392268300056458},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5344340801239014},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.5245155096054077},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5167266726493835},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.46030738949775696},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.42260703444480896},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3959639370441437},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3836634159088135},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.35690969228744507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24782010912895203},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.19632494449615479},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14648014307022095}],"concepts":[{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.7958709001541138},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.6734318733215332},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6689047813415527},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.6622945070266724},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6489227414131165},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.6118266582489014},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5963686108589172},{"id":"https://openalex.org/C183003079","wikidata":"https://www.wikidata.org/wiki/Q1000371","display_name":"Personalization","level":2,"score":0.5713543891906738},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5435729622840881},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5392268300056458},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5344340801239014},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.5245155096054077},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5167266726493835},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.46030738949775696},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.42260703444480896},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3959639370441437},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3836634159088135},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.35690969228744507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24782010912895203},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.19632494449615479},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14648014307022095},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2004.1358839","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358839","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.49000000953674316}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2134849712","https://openalex.org/W2152896392","https://openalex.org/W2154670520","https://openalex.org/W2162546785","https://openalex.org/W2564921634","https://openalex.org/W4248469525","https://openalex.org/W6679846583","https://openalex.org/W6683964721"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W3022525969","https://openalex.org/W1904803855","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W133576369","https://openalex.org/W2014165129","https://openalex.org/W2764789987"],"abstract_inverted_index":{"Application-specific":[0],"standard":[1],"products":[2],"(ASSPs)":[3],"have":[4],"been":[5],"so":[6],"far":[7],"customized":[8],"by":[9,19,50,84],"an":[10],"increasing":[11],"amount":[12],"of":[13,106],"embedded":[14,23,99],"software":[15,59],"or":[16],"very":[17],"recently":[18],"electrically":[20],"and":[21,39,55,58,75,78],"mask-programmable":[22],"gate-arrays.":[24],"The":[25,62,80,98],"solution":[26],"proposed":[27],"in":[28,91],"this":[29],"paper":[30],"addresses":[31],"both":[32],"the":[33,40,70,85,107],"large":[34],"demand":[35],"for":[36,42,73,103],"higher":[37],"flexibility":[38],"need":[41],"fast":[43],"product":[44],"turn-around":[45],"time.":[46],"This":[47],"is":[48,65,87],"achieved":[49],"using":[51],"single-via":[52],"programmable":[53],"logic":[54,101],"consistent":[56],"hardware":[57],"co-design":[60],"flow.":[61],"system":[63,86,108],"architecture":[64],"discussed":[66],"as":[67,69],"well":[68],"design":[71,77],"flows":[72],"pre-":[74],"post-silicon":[76],"customization.":[79],"silicon":[81],"area":[82],"required":[83],"23":[88],"mm/sup":[89],"2/":[90],"a":[92],"0.13":[93],"/spl":[94],"mu/m":[95],"CMOS":[96],"technology.":[97],"via-programmable":[100],"accounts":[102],"about":[104],"30%":[105],"area.":[109]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}