{"id":"https://openalex.org/W2565121823","doi":"https://doi.org/10.1109/cicc.2004.1358788","title":"A 3D mixed-mode ESD protection circuit simulation-design methodology","display_name":"A 3D mixed-mode ESD protection circuit simulation-design methodology","publication_year":2004,"publication_date":"2004-11-30","ids":{"openalex":"https://openalex.org/W2565121823","doi":"https://doi.org/10.1109/cicc.2004.1358788","mag":"2565121823"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2004.1358788","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084257637","display_name":"Hao Xie","orcid":"https://orcid.org/0000-0002-3564-9091"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Xie","raw_affiliation_strings":["Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111939932","display_name":"R. Zhan","orcid":"https://orcid.org/0009-0003-9206-5863"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Zhan","raw_affiliation_strings":["Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052172658","display_name":"Haigang Feng","orcid":"https://orcid.org/0000-0002-8377-1171"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Feng","raw_affiliation_strings":["Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081971104","display_name":"G. Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Chen","raw_affiliation_strings":["Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060916409","display_name":"A. Wang","orcid":null},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Wang","raw_affiliation_strings":["Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Electronics laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111887218","display_name":"R. Gafiteanu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210088951","display_name":"Synopsys (United States)","ror":"https://ror.org/013by2m91","country_code":"US","type":"company","lineage":["https://openalex.org/I4210088951"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Gafiteanu","raw_affiliation_strings":["Synopsys, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Synopsys, Inc., Sunnyvale, CA, USA","institution_ids":["https://openalex.org/I4210088951"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.35138332,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"243","last_page":"246"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electrostatic-discharge","display_name":"Electrostatic discharge","score":0.9229008555412292},{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.6834694147109985},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6333260536193848},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.562168300151825},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.47433584928512573},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45806506276130676},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.41485071182250977},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3822067379951477},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3441349267959595},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3338494896888733},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.22383949160575867},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.13254734873771667},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.07233262062072754}],"concepts":[{"id":"https://openalex.org/C205483674","wikidata":"https://www.wikidata.org/wiki/Q3574961","display_name":"Electrostatic discharge","level":3,"score":0.9229008555412292},{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.6834694147109985},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6333260536193848},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.562168300151825},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.47433584928512573},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45806506276130676},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.41485071182250977},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3822067379951477},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3441349267959595},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3338494896888733},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.22383949160575867},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.13254734873771667},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.07233262062072754},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2004.1358788","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2004.1358788","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1433377089","https://openalex.org/W2100286024","https://openalex.org/W2130390619","https://openalex.org/W2159976098","https://openalex.org/W4239662273","https://openalex.org/W6628515055","https://openalex.org/W6679474296"],"related_works":["https://openalex.org/W2083784839","https://openalex.org/W2565121823","https://openalex.org/W1818002215","https://openalex.org/W4389888235","https://openalex.org/W2171232454","https://openalex.org/W1625266818","https://openalex.org/W2123028129","https://openalex.org/W1512125785","https://openalex.org/W2913967916","https://openalex.org/W3115603471"],"abstract_inverted_index":{"Electrostatic":[0],"discharge":[1],"(ESD)":[2],"is":[3,12],"a":[4,23],"serious":[5],"IC":[6],"reliability":[7],"problem.":[8],"On-chip":[9],"ESD":[10,18,27,33,37],"protection":[11,28,38],"used":[13],"to":[14],"protect":[15],"ICs":[16],"against":[17],"damage.":[19],"This":[20],"paper":[21],"presents":[22],"real":[24],"3D":[25],"mixed-mode":[26],"circuit":[29],"simulation-design":[30],"methodology":[31],"for":[32],"design":[34,39],"prediction.":[35],"Practical":[36],"examples":[40],"in":[41],"0.35":[42],"/spl":[43],"mu/m":[44],"BiCMOS":[45],"are":[46],"given.":[47]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}