{"id":"https://openalex.org/W1538922477","doi":"https://doi.org/10.1109/cicc.2003.1249356","title":"SoC implementation issues for synthesizable embedded programmable logic cores","display_name":"SoC implementation issues for synthesizable embedded programmable logic cores","publication_year":2004,"publication_date":"2004-01-23","ids":{"openalex":"https://openalex.org/W1538922477","doi":"https://doi.org/10.1109/cicc.2003.1249356","mag":"1538922477"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2003.1249356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2003.1249356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059230162","display_name":"Jianlu Wu","orcid":"https://orcid.org/0009-0003-3066-2611"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J.C.H. Wu","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada","The University of British Columbia, Vancouver, BC, CA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"The University of British Columbia, Vancouver, BC, CA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023192836","display_name":"V. Aken'Ova","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"V. Aken'Ova","raw_affiliation_strings":["Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013246362","display_name":"Steven J. E. Wilton","orcid":"https://orcid.org/0000-0002-1241-6690"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S.J.E. Wilton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111280120","display_name":"R. Saleh","orcid":null},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"R. Saleh","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, B.C, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I141945490"],"apc_list":null,"apc_paid":null,"fwci":1.442,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.78722457,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"45","last_page":"48"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.724521279335022},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6293729543685913},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.6131311058998108},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5981723666191101},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5820909142494202},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.580251932144165},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5389567017555237},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5347145199775696},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.44641104340553284},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4394332468509674},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.437328040599823},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42895275354385376},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.4235770106315613},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4233604669570923},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.08664438128471375},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.07577484846115112}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.724521279335022},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6293729543685913},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.6131311058998108},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5981723666191101},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5820909142494202},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.580251932144165},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5389567017555237},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5347145199775696},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.44641104340553284},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4394332468509674},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.437328040599823},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42895275354385376},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.4235770106315613},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4233604669570923},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.08664438128471375},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.07577484846115112}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/cicc.2003.1249356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2003.1249356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003.","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.224.9234","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.224.9234","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.ubc.ca/%7Estevew/papers/pdf/cicc03.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2099502153","https://openalex.org/W2102872410","https://openalex.org/W2109656299","https://openalex.org/W2147419146","https://openalex.org/W2149518767","https://openalex.org/W2152896392","https://openalex.org/W2564921634"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W1904803855","https://openalex.org/W1522436970","https://openalex.org/W2490069675","https://openalex.org/W2102777336","https://openalex.org/W2197466303","https://openalex.org/W3105918491","https://openalex.org/W2972060505"],"abstract_inverted_index":{"As":[0],"integrated":[1,74,107],"circuits":[2],"have":[3],"become":[4,16],"more":[5,7,17,19],"and":[6,18,109,117],"complex,":[8],"the":[9,38,70,92,97,100,103,106],"ability":[10,22],"to":[11,48,102],"make":[12],"post-fabrication":[13],"changes":[14],"will":[15],"attractive.":[20],"This":[21],"can":[23,58],"be":[24,59],"realized":[25],"using":[26,61],"programmable":[27,54,81],"logic":[28,55,82],"cores.":[29],"Currently,":[30],"such":[31,78],"cores":[32],"are":[33],"available":[34],"from":[35],"vendors":[36],"in":[37],"form":[39],"of":[40,72,94,99,105],"a":[41,50,79],"\"hard\"":[42],"layout.":[43],"An":[44],"alternative":[45],"approach":[46],"is":[47],"use":[49],"\"soft\",":[51],"or":[52],"synthesizable":[53,80],"core":[56,95,101],"that":[57,76,89],"synthesized":[60],"standard":[62],"library":[63],"cells.":[64],"In":[65],"this":[66],"paper,":[67],"we":[68],"describe":[69],"design":[71],"an":[73],"circuit":[75],"incorporates":[77],"core.":[83],"We":[84,113],"focus":[85],"on":[86],"implementation":[87],"issues":[88],"arose;":[90],"specifically,":[91],"choice":[93],"size,":[96],"connection":[98],"rest":[104],"circuit,":[108],"clock":[110],"tree":[111],"synthesis.":[112],"also":[114],"present":[115],"area":[116],"delay":[118],"overhead":[119],"results.":[120]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}