{"id":"https://openalex.org/W2106784640","doi":"https://doi.org/10.1109/cicc.2002.1012764","title":"A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay","display_name":"A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2106784640","doi":"https://doi.org/10.1109/cicc.2002.1012764","mag":"2106784640"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2002.1012764","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012764","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100809620","display_name":"Hsiang-Hui Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Hsiang-Hui Chang","raw_affiliation_strings":["Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080392236","display_name":"Jyh\u2010Woei Lin","orcid":"https://orcid.org/0000-0001-6875-0172"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jyh-Woei Lin","raw_affiliation_strings":["Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064663968","display_name":"Shen-Iuan Liu","orcid":"https://orcid.org/0000-0002-3765-2948"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shen-Iuan Liu","raw_affiliation_strings":["Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering & Graduate Institute of Electronic Engineering, National Taiwan University, Taipei, Taiwan","institution_ids":["https://openalex.org/I16733864"]},{"raw_affiliation_string":"Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I16733864"],"apc_list":null,"apc_paid":null,"fwci":0.4308,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59922277,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9908000230789185,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8597622513771057},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5864712595939636},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.5334112048149109},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.5038298964500427},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4688602089881897},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.37480592727661133},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.32069724798202515},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.21488457918167114},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13974007964134216}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8597622513771057},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5864712595939636},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.5334112048149109},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.5038298964500427},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4688602089881897},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.37480592727661133},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.32069724798202515},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.21488457918167114},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13974007964134216}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/cicc.2002.1012764","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012764","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"},{"id":"pmh:oai:140.112.114.62:246246/2007041910021169","is_oa":false,"landing_page_url":"http://ntur.lib.ntu.edu.tw//handle/246246/2007041910021169","pdf_url":null,"source":{"id":"https://openalex.org/S4306402491","display_name":"NTUR (\u81fa\u7063\u6a5f\u69cb\u5178\u85cf)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I16733864","host_organization_name":"National Taiwan University","host_organization_lineage":["https://openalex.org/I16733864"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7799999713897705}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1580873078","https://openalex.org/W1675735732","https://openalex.org/W2059008798","https://openalex.org/W2099759033","https://openalex.org/W2102720893","https://openalex.org/W2114953806","https://openalex.org/W2118721819","https://openalex.org/W2138615880","https://openalex.org/W2148690934","https://openalex.org/W2490904451","https://openalex.org/W2587442922","https://openalex.org/W6681792707"],"related_works":["https://openalex.org/W2139484866","https://openalex.org/W2052495274","https://openalex.org/W1480207378","https://openalex.org/W2166100863","https://openalex.org/W2354050524","https://openalex.org/W2900271051","https://openalex.org/W2976219355","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W3177439118"],"abstract_inverted_index":{"In":[0],"this":[1,34],"paper,":[2],"a":[3,10,71,91,114],"wide":[4],"range":[5,32,45,131],"delay-locked":[6],"loop":[7],"(DLL)":[8],"with":[9],"fixed":[11],"latency":[12,141],"of":[13,33,46,70,80,105,117],"one":[14,144],"clock":[15,145],"cycle":[16],"is":[17,77,132,142],"proposed.":[18],"Using":[19],"the":[20,25,29,38,47,65,78,85,99,128,140,148,153],"phase":[21],"selection":[22],"circuit":[23,27],"and":[24,36,61,67,75,112,139],"start-controlled":[26],"enlarges":[28],"operating":[30,43,129,150],"frequency":[31,44,130,151],"DLL":[35,48,100],"eliminates":[37],"harmonic":[39],"locking":[40],"problems.":[41],"The":[42,123],"can":[49],"be":[50],"from":[51,133],"1/T/sub":[52],"Dmin/":[53,60],"to":[54,136],"1/(N/spl":[55],"times/T/sub":[56],"Dmax/),":[57],"where":[58],"T/sub":[59,62],"Dmax/":[63],"are":[64],"minimum":[66],"maximum":[68,115,154],"delay":[69,72,81,86],"cell,":[73],"respectively,":[74],"N":[76],"number":[79],"cells":[82],"used":[83],"in":[84,90],"line":[87],"theoretically.":[88],"Fabricated":[89],"0.35":[92],"/spl":[93,107,110],"mu/m":[94,111],"1P3M":[95],"standard":[96],"CMOS":[97],"process,":[98],"occupies":[101],"an":[102],"active":[103],"area":[104],"880":[106],"mu/m/spl":[108],"times/515":[109],"consumes":[113],"power":[116],"132":[118],"mW":[119],"at":[120],"130":[121,137],"MHz.":[122],"measurement":[124],"results":[125],"show":[126],"that":[127],"6":[134],"MHz":[135,138],"just":[143],"cycle.":[146],"From":[147],"entire":[149],"range,":[152],"r.m.s.":[155],"jitter":[156],"would":[157],"not":[158],"exceed":[159],"25":[160],"ps.":[161]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}