{"id":"https://openalex.org/W2134904708","doi":"https://doi.org/10.1109/cicc.2002.1012758","title":"Loop-based interconnect modeling and optimization approach for multi-GHz clock network design","display_name":"Loop-based interconnect modeling and optimization approach for multi-GHz clock network design","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2134904708","doi":"https://doi.org/10.1109/cicc.2002.1012758","mag":"2134904708"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2002.1012758","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103362157","display_name":"Xuejue Huang","orcid":"https://orcid.org/0000-0002-3392-8986"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Xuejue Huang","raw_affiliation_strings":["EECS Department, University of California, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054155143","display_name":"P.J. Restle","orcid":"https://orcid.org/0000-0002-3124-4265"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]},{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"P. Restle","raw_affiliation_strings":["EECS Department, University of California, Berkeley, CA, USA","IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086941799","display_name":"T. Bucelot","orcid":null},"institutions":[{"id":"https://openalex.org/I4210114115","display_name":"IBM Research - Thomas J. Watson Research Center","ror":"https://ror.org/0265w5591","country_code":"US","type":"facility","lineage":["https://openalex.org/I1341412227","https://openalex.org/I4210114115"]},{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"T. Bucelot","raw_affiliation_strings":["EECS Department, University of California, Berkeley, CA, USA","IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]},{"raw_affiliation_string":"IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA","institution_ids":["https://openalex.org/I4210114115"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100740019","display_name":"Yu Cao","orcid":"https://orcid.org/0000-0001-6968-1180"},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yu Cao","raw_affiliation_strings":["EECS Department, University of California, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063366384","display_name":"Tsu\u2010Jae King","orcid":null},"institutions":[{"id":"https://openalex.org/I95457486","display_name":"University of California, Berkeley","ror":"https://ror.org/01an7q238","country_code":"US","type":"education","lineage":["https://openalex.org/I95457486"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tsu-Jae King","raw_affiliation_strings":["EECS Department, University of California, Berkeley, CA, USA"],"affiliations":[{"raw_affiliation_string":"EECS Department, University of California, Berkeley, CA, USA","institution_ids":["https://openalex.org/I95457486"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5103362157"],"corresponding_institution_ids":["https://openalex.org/I95457486"],"apc_list":null,"apc_paid":null,"fwci":1.7386,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.85375204,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"19","last_page":"22"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.833349347114563},{"id":"https://openalex.org/keywords/inductance","display_name":"Inductance","score":0.7049926519393921},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6566601991653442},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5940780639648438},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5793318152427673},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5213066935539246},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.4983179569244385},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45052605867385864},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.4434855580329895},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.43462955951690674},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.2842062711715698},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.274977445602417},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2247818112373352},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.20557579398155212},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11218732595443726},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.10634362697601318},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.10309547185897827},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09684711694717407}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.833349347114563},{"id":"https://openalex.org/C29210110","wikidata":"https://www.wikidata.org/wiki/Q177897","display_name":"Inductance","level":3,"score":0.7049926519393921},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6566601991653442},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5940780639648438},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5793318152427673},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5213066935539246},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.4983179569244385},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45052605867385864},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.4434855580329895},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.43462955951690674},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.2842062711715698},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.274977445602417},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2247818112373352},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.20557579398155212},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11218732595443726},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.10634362697601318},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.10309547185897827},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09684711694717407},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2002.1012758","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012758","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.7099999785423279}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1507443765","https://openalex.org/W2017416618","https://openalex.org/W2026188268","https://openalex.org/W2075891646","https://openalex.org/W2125580855","https://openalex.org/W2147451535","https://openalex.org/W2149470799","https://openalex.org/W2154941678","https://openalex.org/W2157763958","https://openalex.org/W2167232953","https://openalex.org/W2168224801","https://openalex.org/W2169468042","https://openalex.org/W2567262142","https://openalex.org/W4238248195","https://openalex.org/W6654707124"],"related_works":["https://openalex.org/W2141173693","https://openalex.org/W260689458","https://openalex.org/W2050988079","https://openalex.org/W23415020","https://openalex.org/W2520249613","https://openalex.org/W2565835957","https://openalex.org/W3129840721","https://openalex.org/W2027268352","https://openalex.org/W1987455272","https://openalex.org/W2767138966"],"abstract_inverted_index":{"An":[0],"efficient":[1],"loop-based":[2],"interconnect":[3],"modeling":[4],"methodology":[5],"is":[6],"proposed":[7],"for":[8],"multi-GHz":[9],"clock":[10],"network":[11],"design.":[12],"High":[13],"frequency":[14],"effects,":[15],"including":[16],"inductance":[17],"and":[18,32],"proximity":[19],"effects":[20],"are":[21,25],"captured.":[22],"The":[23],"results":[24],"validated":[26],"through":[27],"comparisons":[28],"with":[29],"electromagnetic":[30],"simulations":[31],"measured":[33],"data":[34],"taken":[35],"from":[36],"a":[37],"Power4":[38],"chip.":[39]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
