{"id":"https://openalex.org/W2152896392","doi":"https://doi.org/10.1109/cicc.2002.1012757","title":"A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O","display_name":"A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA and customisable I/O","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2152896392","doi":"https://doi.org/10.1109/cicc.2002.1012757","mag":"2152896392"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2002.1012757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033815891","display_name":"M. Borgatti","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Borgatti","raw_affiliation_strings":["Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057600694","display_name":"F. Lertora","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Lertora","raw_affiliation_strings":["Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072229416","display_name":"B. For\u00eat","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"B. Foret","raw_affiliation_strings":["Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5042947591","display_name":"L. Cal\u00ec","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Cali","raw_affiliation_strings":["Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy"],"affiliations":[{"raw_affiliation_string":"Innovative Systems Design, NVM-DP, Central R&D, STMicroelectronics, Milan, Italy","institution_ids":["https://openalex.org/I4210154781"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5033815891"],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":1.7608,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.85835363,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"13","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8344337940216064},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.816920280456543},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.7849217653274536},{"id":"https://openalex.org/keywords/extensibility","display_name":"Extensibility","score":0.76276695728302},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7119687795639038},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6194256544113159},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5175532698631287},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5114444494247437},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4697214663028717},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42796188592910767},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.4195018708705902},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.41134753823280334},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2582096457481384}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8344337940216064},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.816920280456543},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.7849217653274536},{"id":"https://openalex.org/C32833848","wikidata":"https://www.wikidata.org/wiki/Q4115054","display_name":"Extensibility","level":2,"score":0.76276695728302},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7119687795639038},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6194256544113159},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5175532698631287},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5114444494247437},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4697214663028717},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42796188592910767},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.4195018708705902},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.41134753823280334},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2582096457481384}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2002.1012757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2002.1012757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.4000000059604645,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1981176352","https://openalex.org/W2068041061","https://openalex.org/W2122068936","https://openalex.org/W2136584940","https://openalex.org/W2154670520","https://openalex.org/W2165099691","https://openalex.org/W2168244800","https://openalex.org/W2169601811","https://openalex.org/W2171697422","https://openalex.org/W3146150975"],"related_works":["https://openalex.org/W2471791811","https://openalex.org/W4256272048","https://openalex.org/W1980352715","https://openalex.org/W2160342394","https://openalex.org/W2185423317","https://openalex.org/W2090940121","https://openalex.org/W2132729873","https://openalex.org/W1589728323","https://openalex.org/W1502060307","https://openalex.org/W2073444830"],"abstract_inverted_index":{"A":[0],"system-chip":[1],"targeting":[2],"image":[3],"and":[4,7,37,41,49,53,59,82,85],"voice":[5],"processing":[6],"recognition":[8],"application":[9],"domains":[10],"is":[11,72,94],"implemented":[12],"as":[13,74,76],"a":[14,35,42,99],"representative":[15],"of":[16,19,69,112],"the":[17,64,70,77,92,113],"potential":[18],"using":[20],"programmable":[21],"logic":[22],"in":[23,98],"system":[24,71,93,114],"design.":[25],"It":[26],"features":[27],"an":[28],"embedded":[29,44,65,106],"reconfigurable":[30],"processor":[31,39],"built":[32],"by":[33,62,91],"joining":[34],"configurable":[36],"extensible":[38],"core":[40],"SRAM-based":[43],"FPGA.":[45,66],"Application-specific":[46],"bus-mapped":[47],"coprocessors":[48],"flexible":[50],"I/O":[51],"peripherals":[52],"interfaces":[54],"can":[55],"also":[56],"be":[57],"added":[58],"dynamically":[60],"modified":[61],"reconfiguring":[63],"The":[67,87,105],"architecture":[68],"discussed":[73],"well":[75],"design":[78,84],"flows":[79],"for":[80,109],"pre-":[81],"post-silicon":[83],"customisation.":[86],"silicon":[88],"area":[89],"required":[90],"20":[95],"mm/sup":[96],"2/":[97],"0.18":[100],"/spl":[101],"mu/m":[102],"CMOS":[103],"technology.":[104],"FPGA":[107],"accounts":[108],"about":[110],"40%":[111],"area.":[115]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
