{"id":"https://openalex.org/W2125401147","doi":"https://doi.org/10.1109/cicc.2000.852715","title":"Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience","display_name":"Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience","publication_year":2002,"publication_date":"2002-11-07","ids":{"openalex":"https://openalex.org/W2125401147","doi":"https://doi.org/10.1109/cicc.2000.852715","mag":"2125401147"},"language":"en","primary_location":{"id":"doi:10.1109/cicc.2000.852715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2000.852715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044401095","display_name":"Eileen You","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"E. You","raw_affiliation_strings":["Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081586065","display_name":"Swee Yew Choe","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Swee Yew Choe","raw_affiliation_strings":["Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081717979","display_name":"Chin Kim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Chin Kim","raw_affiliation_strings":["Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040747560","display_name":"L. Varadadesikan","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"L. Varadadesikan","raw_affiliation_strings":["Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5021045457","display_name":"K. Aingaran","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K. Aingaran","raw_affiliation_strings":["Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040245683","display_name":"J. MacDonald","orcid":"https://orcid.org/0000-0001-5139-6533"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. MacDonald","raw_affiliation_strings":["Mentor Graphics Corporation, USA","Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, USA","institution_ids":["https://openalex.org/I4210156212"]},{"raw_affiliation_string":"Sun MicroSystems, Inc.orporated, Palo Alto, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5044401095"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3394,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.60597666,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"3","issue":null,"first_page":"491","last_page":"494"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.652811586856842},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6440073251724243},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5985844135284424},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5858163237571716},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5501022934913635},{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.5094755291938782},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4937678277492523},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.49049490690231323},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4797859787940979},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4782811105251312},{"id":"https://openalex.org/keywords/extraction","display_name":"Extraction (chemistry)","score":0.45960214734077454},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2574072778224945},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20899206399917603},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.18079239130020142},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08033439517021179},{"id":"https://openalex.org/keywords/mechanical-engineering","display_name":"Mechanical engineering","score":0.07049810886383057}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.652811586856842},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6440073251724243},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5985844135284424},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5858163237571716},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5501022934913635},{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.5094755291938782},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4937678277492523},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.49049490690231323},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4797859787940979},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4782811105251312},{"id":"https://openalex.org/C4725764","wikidata":"https://www.wikidata.org/wiki/Q844704","display_name":"Extraction (chemistry)","level":2,"score":0.45960214734077454},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2574072778224945},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20899206399917603},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.18079239130020142},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08033439517021179},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.07049810886383057},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C43617362","wikidata":"https://www.wikidata.org/wiki/Q170050","display_name":"Chromatography","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cicc.2000.852715","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cicc.2000.852715","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W82686468","https://openalex.org/W2007841765","https://openalex.org/W2055608259","https://openalex.org/W2085889437","https://openalex.org/W2093686670","https://openalex.org/W2118402135","https://openalex.org/W2143746319","https://openalex.org/W2146305994","https://openalex.org/W2157089032","https://openalex.org/W4231124869","https://openalex.org/W4240411326","https://openalex.org/W4256356575","https://openalex.org/W6837835293"],"related_works":["https://openalex.org/W4387917714","https://openalex.org/W2885948601","https://openalex.org/W2170939617","https://openalex.org/W129745824","https://openalex.org/W4255141013","https://openalex.org/W4312992159","https://openalex.org/W2110634429","https://openalex.org/W2157190039","https://openalex.org/W1987127550","https://openalex.org/W3094423394"],"abstract_inverted_index":{"This":[0,49],"paper":[1],"discusses":[2],"accuracy":[3],"issues":[4],"in":[5,45],"parasitic":[6,25],"extraction":[7,68],"for":[8,53],"the":[9,21,24,31,54,63,67],"design":[10,47],"of":[11,33,66],"multimillion-transistor":[12],"integrated":[13],"circuits.":[14],"The":[15,36],"methodology":[16,50,69],"reported":[17],"aims":[18],"at":[19],"reducing":[20],"gap":[22],"between":[23],"values":[26],"estimated":[27],"during":[28],"implementation":[29],"and":[30,78],"results":[32,61],"post-layout":[34],"extraction.":[35],"objective":[37],"is":[38],"to":[39],"obtain":[40],"progressively":[41],"refined":[42],"interconnect":[43,71],"models":[44],"hierarchical":[46],"flows.":[48],"was":[51],"developed":[52],"800":[55],"MHz":[56],"UltraSPARC-III":[57],"microprocessor.":[58],"Our":[59],"experimental":[60],"demonstrate":[62],"profound":[64],"impact":[65],"on":[70],"modeling":[72],"as":[73,75],"well":[74],"subsequent":[76],"timing":[77],"noise":[79],"analyses.":[80]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
