{"id":"https://openalex.org/W4237444750","doi":"https://doi.org/10.1109/cgo.2019.8661195","title":"Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures","display_name":"Translating Traditional SIMD Instructions to Vector Length Agnostic Architectures","publication_year":2019,"publication_date":"2019-02-01","ids":{"openalex":"https://openalex.org/W4237444750","doi":"https://doi.org/10.1109/cgo.2019.8661195"},"language":"en","primary_location":{"id":"doi:10.1109/cgo.2019.8661195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cgo.2019.8661195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031659418","display_name":"Sheng\u2010Yu Fu","orcid":null},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Sheng-Yu Fu","raw_affiliation_strings":["National Taiwan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017207899","display_name":"Wei\u2010Chung Hsu","orcid":"https://orcid.org/0000-0002-0833-7981"},"institutions":[{"id":"https://openalex.org/I16733864","display_name":"National Taiwan University","ror":"https://ror.org/05bqach95","country_code":"TW","type":"education","lineage":["https://openalex.org/I16733864"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wei-Chung Hsu","raw_affiliation_strings":["National Taiwan University, Taiwan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Taiwan University, Taiwan","institution_ids":["https://openalex.org/I16733864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.30552038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"275","last_page":"275"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9718999862670898,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9718999862670898,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13293","display_name":"Engineering and Test Systems","score":0.9609000086784363,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9538000226020813,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simd","display_name":"SIMD","score":0.9316173791885376},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7966179251670837},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7038707733154297},{"id":"https://openalex.org/keywords/x86","display_name":"x86","score":0.6365398168563843},{"id":"https://openalex.org/keywords/executable","display_name":"Executable","score":0.6191160082817078},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.538602352142334},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5383068323135376},{"id":"https://openalex.org/keywords/vector-processor","display_name":"Vector processor","score":0.5204039812088013},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2554980218410492},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.21344518661499023},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.15500298142433167}],"concepts":[{"id":"https://openalex.org/C150552126","wikidata":"https://www.wikidata.org/wiki/Q339387","display_name":"SIMD","level":2,"score":0.9316173791885376},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7966179251670837},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7038707733154297},{"id":"https://openalex.org/C170723468","wikidata":"https://www.wikidata.org/wiki/Q182933","display_name":"x86","level":3,"score":0.6365398168563843},{"id":"https://openalex.org/C160145156","wikidata":"https://www.wikidata.org/wiki/Q778586","display_name":"Executable","level":2,"score":0.6191160082817078},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.538602352142334},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5383068323135376},{"id":"https://openalex.org/C161824985","wikidata":"https://www.wikidata.org/wiki/Q919509","display_name":"Vector processor","level":2,"score":0.5204039812088013},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2554980218410492},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.21344518661499023},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.15500298142433167},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cgo.2019.8661195","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cgo.2019.8661195","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2110615297","https://openalex.org/W2129537883","https://openalex.org/W2527376031","https://openalex.org/W2911551207","https://openalex.org/W2030906223","https://openalex.org/W4225987401","https://openalex.org/W4236526691","https://openalex.org/W4226140811","https://openalex.org/W3151122335","https://openalex.org/W2003690377"],"abstract_inverted_index":{"One":[0],"interesting":[1,92],"trend":[2],"of":[3,52,63],"SIMD":[4,64,84],"architecture":[5,88],"is":[6,66],"towards":[7],"Vector":[8,20],"Length":[9],"Agnostic":[10],"(VLA)":[11],"designs.":[12],"For":[13],"example,":[14],"ARM":[15],"new":[16],"vector":[17,25,35,53,77],"ISA,":[18],"Scalable":[19],"Extension":[21],"(SVE),":[22],"and":[23,75,93],"RISC-V":[24],"extension":[26],"are":[27],"adopting":[28],"such":[29,69],"a":[30],"direction.":[31],"VLA":[32,87],"decouples":[33],"the":[34,39,44,57,61],"register":[36],"length":[37],"from":[38],"compiled":[40],"binary":[41],"so":[42],"that":[43],"same":[45],"executable":[46],"could":[47],"run":[48],"on":[49],"different":[50],"implementations":[51],"length.":[54],"However,":[55],"in":[56],"current":[58],"application":[59],"world,":[60],"majority":[62],"code":[65,85],"fixed-length":[67],"based,":[68],"as":[70],"ARM-NEON,":[71],"x86-":[72],"SSE,":[73],"x86-AVX,":[74],"traditional":[76],"machines.":[78],"Therefore,":[79],"how":[80],"to":[81,86],"migrate":[82],"legacy":[83],"would":[89],"be":[90],"an":[91],"important":[94],"technical":[95],"challenge.":[96]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
