{"id":"https://openalex.org/W1554894717","doi":"https://doi.org/10.1109/cgo.2004.1281660","title":"Ispike: A post-link optimizer for the intel architecture","display_name":"Ispike: A post-link optimizer for the intel architecture","publication_year":2004,"publication_date":"2004-06-10","ids":{"openalex":"https://openalex.org/W1554894717","doi":"https://doi.org/10.1109/cgo.2004.1281660","mag":"1554894717"},"language":"en","primary_location":{"id":"doi:10.1109/cgo.2004.1281660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cgo.2004.1281660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Code Generation and Optimization, 2004. CGO 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068589709","display_name":"C.K. Luk","orcid":"https://orcid.org/0009-0009-9938-8327"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Chi-Keung Luk","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, USA","Massachusetts Microprocessor Design Center, Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019781598","display_name":"Robert Muth","orcid":"https://orcid.org/0000-0002-7954-2157"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Muth","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, USA","Massachusetts Microprocessor Design Center, Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112618401","display_name":"Harish Patil","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"H. Patil","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, USA","Massachusetts Microprocessor Design Center, Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019791712","display_name":"Robert Cohn","orcid":"https://orcid.org/0009-0005-7234-4886"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Cohn","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, USA","Massachusetts Microprocessor Design Center, Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040159348","display_name":"Geoff Lowney","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G. Lowney","raw_affiliation_strings":["Massachusetts Microprocessor Design Center, Intel Corporation, USA","Massachusetts Microprocessor Design Center, Intel Corp., USA"],"affiliations":[{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Massachusetts Microprocessor Design Center, Intel Corp., USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5068589709"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.0532,"has_fulltext":false,"cited_by_count":20,"citation_normalized_percentile":{"value":0.75231633,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"15","last_page":"26"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7078567147254944},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.561122715473175},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5373436808586121},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4529236853122711},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3242901563644409}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7078567147254944},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.561122715473175},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5373436808586121},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4529236853122711},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3242901563644409},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cgo.2004.1281660","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cgo.2004.1281660","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"International Symposium on Code Generation and Optimization, 2004. CGO 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W1627759","https://openalex.org/W49852366","https://openalex.org/W1500027417","https://openalex.org/W1947621832","https://openalex.org/W2008015263","https://openalex.org/W2009711341","https://openalex.org/W2024043936","https://openalex.org/W2042708654","https://openalex.org/W2099958604","https://openalex.org/W2116672403","https://openalex.org/W2149918819","https://openalex.org/W2150001879","https://openalex.org/W2153131460","https://openalex.org/W2153228154","https://openalex.org/W2161698662","https://openalex.org/W2183316753","https://openalex.org/W3042530772","https://openalex.org/W3137707395","https://openalex.org/W4205854416","https://openalex.org/W4248045917","https://openalex.org/W4256689451","https://openalex.org/W6602033007","https://openalex.org/W6640724070","https://openalex.org/W6682030157","https://openalex.org/W6683859019","https://openalex.org/W6686234601"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W2390279801","https://openalex.org/W2358668433","https://openalex.org/W2376932109","https://openalex.org/W2001405890","https://openalex.org/W2382290278","https://openalex.org/W2478288626","https://openalex.org/W2350741829","https://openalex.org/W2530322880","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Ispike":[0,109],"is":[1,44,169],"a":[2,28,40],"post-link":[3,24,47,63],"optimizer":[4],"developed":[5],"for":[6,172],"the":[7,52,55,90,98,118,133,140,166],"Intel/spl":[8,134],"reg/":[9,135],"Itanium":[10],"Processor":[11],"Family":[12],"(IPF)":[13],"processors.":[14],"The":[15],"IPF":[16,26,61,91,152],"architecture":[17],"poses":[18],"both":[19],"opportunities":[20],"and":[21,57,85,93,127,138,155],"challenges":[22],"to":[23,34,46],"optimizations.":[25],"offers":[27],"rich":[29],"set":[30],"of":[31,125],"performance":[32,111,153,163,173],"counters":[33,154],"collect":[35],"detailed":[36],"profile":[37],"information":[38],"at":[39],"low":[41],"cost,":[42],"which":[43],"essential":[45],"optimization":[48],"being":[49],"practical.":[50],"At":[51],"same":[53],"time,":[54],"predication":[56],"bundling":[58],"features":[59],"on":[60,69,117],"make":[62],"code":[64,79],"transformation":[65],"more":[66],"challenging":[67],"than":[68],"other":[70],"architectures.":[71],"In":[72],"Ispike,":[73],"we":[74,106],"have":[75],"implemented":[76],"optimizations":[77],"like":[78],"layout,":[80,84],"instruction":[81],"prefetching,":[82],"data":[83,86],"prefetching":[87],"that":[88,95,108,147],"exploit":[89],"advantages,":[92],"strategies":[94],"cope":[96],"with":[97,122],"IPF-specific":[99],"challenges.":[100],"Using":[101],"SPEC":[102],"CINT2000":[103],"as":[104,113,115],"benchmarks,":[105],"show":[107],"improves":[110],"by":[112,132,139],"much":[114],"40%":[116],"ltanium/spl":[119],"reg/2":[120],"processor,":[121],"average":[123],"improvement":[124],"8.5%":[126],"9.9%":[128],"over":[129],"executables":[130],"generated":[131],"Electron":[136],"compiler":[137],"Gcc":[141],"compiler,":[142],"respectively.":[143],"We":[144],"also":[145],"demonstrate":[146],"statistical":[148],"profiles":[149,157],"collected":[150,158],"via":[151,159],"complete":[156],"instrumentation":[160],"produce":[161],"equal":[162],"benefit,":[164],"but":[165],"profiling":[167],"overhead":[168],"significantly":[170],"lower":[171],"counters.":[174]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}