{"id":"https://openalex.org/W2118261449","doi":"https://doi.org/10.1109/cec.2014.6900565","title":"Optimization of combinational logic circuits through decomposition of truth table and evolution of sub-circuits","display_name":"Optimization of combinational logic circuits through decomposition of truth table and evolution of sub-circuits","publication_year":2014,"publication_date":"2014-07-01","ids":{"openalex":"https://openalex.org/W2118261449","doi":"https://doi.org/10.1109/cec.2014.6900565","mag":"2118261449"},"language":"en","primary_location":{"id":"doi:10.1109/cec.2014.6900565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2014.6900565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Congress on Evolutionary Computation (CEC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082077462","display_name":"Francisco A. L. Manfrini","orcid":null},"institutions":[{"id":"https://openalex.org/I101100930","display_name":"Universidade Federal de Juiz de Fora","ror":"https://ror.org/04yqw9c44","country_code":"BR","type":"education","lineage":["https://openalex.org/I101100930"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Francisco Manfrini","raw_affiliation_strings":["Universidade Federal de Juiz de Fora, Juiz de Fora, MG, BR","Fed. Inst. of Sci. & Technol. of the Southeast of Minas Gerais, Fed. Univ. of Juiz de Fora, Juiz de Fora, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Juiz de Fora, Juiz de Fora, MG, BR","institution_ids":["https://openalex.org/I101100930"]},{"raw_affiliation_string":"Fed. Inst. of Sci. & Technol. of the Southeast of Minas Gerais, Fed. Univ. of Juiz de Fora, Juiz de Fora, Brazil","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052002490","display_name":"H\u00e9lio J. C. Barbosa","orcid":"https://orcid.org/0000-0001-5810-7554"},"institutions":[{"id":"https://openalex.org/I4210142352","display_name":"Laborat\u00f3rio Nacional de Computa\u00e7\u00e3o Cient\u00edfica","ror":"https://ror.org/0498ekt05","country_code":"BR","type":"government","lineage":["https://openalex.org/I4210142352"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Helio J.C. Barbosa","raw_affiliation_strings":["National Lab. for Scientific Computing, Petr\u00f3polis, RJ, Brazil","Nat. Lab. for Sci. Comput., Petro\u0301polis, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"National Lab. for Scientific Computing, Petr\u00f3polis, RJ, Brazil","institution_ids":["https://openalex.org/I4210142352"]},{"raw_affiliation_string":"Nat. Lab. for Sci. Comput., Petro\u0301polis, Brazil","institution_ids":["https://openalex.org/I4210142352"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5009613609","display_name":"Heder S. Bernardino","orcid":"https://orcid.org/0000-0003-2012-7802"},"institutions":[{"id":"https://openalex.org/I101100930","display_name":"Universidade Federal de Juiz de Fora","ror":"https://ror.org/04yqw9c44","country_code":"BR","type":"education","lineage":["https://openalex.org/I101100930"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Heder S. Bernardino","raw_affiliation_strings":["Universidade Federal de Juiz de Fora, Juiz de Fora, MG, BR","Fed. Univ. of Juiz de Fora, Juiz de Fora, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Universidade Federal de Juiz de Fora, Juiz de Fora, MG, BR","institution_ids":["https://openalex.org/I101100930"]},{"raw_affiliation_string":"Fed. Univ. of Juiz de Fora, Juiz de Fora, Brazil","institution_ids":["https://openalex.org/I101100930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.6203,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.68709945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"6","issue":null,"first_page":"945","last_page":"950"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7688063979148865},{"id":"https://openalex.org/keywords/truth-table","display_name":"Truth table","score":0.7348426580429077},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6959246397018433},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.6802537441253662},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6176718473434448},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5941191911697388},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5862651467323303},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5520541667938232},{"id":"https://openalex.org/keywords/heuristics","display_name":"Heuristics","score":0.5462883710861206},{"id":"https://openalex.org/keywords/boolean-circuit","display_name":"Boolean circuit","score":0.5457106232643127},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5005035400390625},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4607822000980377},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43828386068344116},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.15573403239250183},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15367922186851501},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09817174077033997}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7688063979148865},{"id":"https://openalex.org/C56949724","wikidata":"https://www.wikidata.org/wiki/Q219079","display_name":"Truth table","level":2,"score":0.7348426580429077},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6959246397018433},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.6802537441253662},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6176718473434448},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5941191911697388},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5862651467323303},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5520541667938232},{"id":"https://openalex.org/C127705205","wikidata":"https://www.wikidata.org/wiki/Q5748245","display_name":"Heuristics","level":2,"score":0.5462883710861206},{"id":"https://openalex.org/C141796577","wikidata":"https://www.wikidata.org/wiki/Q837479","display_name":"Boolean circuit","level":3,"score":0.5457106232643127},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5005035400390625},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4607822000980377},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43828386068344116},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.15573403239250183},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15367922186851501},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09817174077033997},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cec.2014.6900565","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2014.6900565","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE Congress on Evolutionary Computation (CEC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322025","display_name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","ror":"https://ror.org/03swz6y49"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W63550369","https://openalex.org/W1486894692","https://openalex.org/W1604160780","https://openalex.org/W1680086042","https://openalex.org/W1735847004","https://openalex.org/W1967457788","https://openalex.org/W1981369758","https://openalex.org/W1985888963","https://openalex.org/W2018094844","https://openalex.org/W2032511682","https://openalex.org/W2039140951","https://openalex.org/W2062011691","https://openalex.org/W2068422506","https://openalex.org/W2079225069","https://openalex.org/W2118131845","https://openalex.org/W2122274805","https://openalex.org/W2130913538","https://openalex.org/W2135060934","https://openalex.org/W2138368455","https://openalex.org/W2497850983","https://openalex.org/W4233183865","https://openalex.org/W6602574690","https://openalex.org/W6645306271"],"related_works":["https://openalex.org/W1939541994","https://openalex.org/W573531811","https://openalex.org/W818963952","https://openalex.org/W2499931839","https://openalex.org/W2110968362","https://openalex.org/W4390345338","https://openalex.org/W4238178324","https://openalex.org/W1621928919","https://openalex.org/W573124066","https://openalex.org/W2146663621"],"abstract_inverted_index":{"In":[0],"this":[1],"work,":[2],"a":[3,35],"genetic":[4],"algorithm":[5],"was":[6,77],"used":[7,104],"to":[8,62,107],"design":[9,92,108],"combinational":[10],"logic":[11,22],"circuits":[12,31],"(CLCs),":[13],"with":[14,54,79,87],"the":[15,19,25,39,42,47,55,63,67,72,97],"goal":[16],"of":[17,21,41,71],"minimizing":[18],"number":[20],"elements":[23],"in":[24,58,100],"circuit.":[26,43],"A":[27],"new":[28],"coding":[29],"for":[30],"is":[32],"proposed":[33],"using":[34,90],"multiplexer":[36],"(MUX)":[37],"at":[38],"output":[40],"This":[44],"MUX":[45],"divides":[46],"truth":[48],"table":[49],"into":[50],"two":[51,68],"distinct":[52],"parts,":[53],"evolution":[56],"occurring":[57],"three":[59],"sub-circuits":[60],"connected":[61],"control":[64],"input":[65],"and":[66],"data":[69],"inputs":[70],"MUX.":[73],"The":[74,83],"methodology":[75],"presented":[76],"tested":[78],"some":[80],"benchmark":[81],"circuits.":[82],"results":[84,98],"were":[85],"compared":[86],"those":[88],"obtained":[89],"traditional":[91],"methods,":[93],"as":[94,96],"well":[95],"found":[99],"other":[101],"articles,":[102],"which":[103],"different":[105],"heuristics":[106],"CLCs.":[109]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
