{"id":"https://openalex.org/W2136414072","doi":"https://doi.org/10.1109/cec.2006.1688291","title":"Optimized Memory Assignment for DSPs","display_name":"Optimized Memory Assignment for DSPs","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2136414072","doi":"https://doi.org/10.1109/cec.2006.1688291","mag":"2136414072"},"language":"en","primary_location":{"id":"doi:10.1109/cec.2006.1688291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2006.1688291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Conference on Evolutionary Computation","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5068888605","display_name":"Gary Gr\u00e9wal","orcid":"https://orcid.org/0000-0003-0845-6929"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G. Grewal","raw_affiliation_strings":["Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5055713873","display_name":"Stelian Coros","orcid":"https://orcid.org/0000-0001-6604-4784"},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"S. Coros","raw_affiliation_strings":["Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113565674","display_name":"D.K. Banerji","orcid":null},"institutions":[{"id":"https://openalex.org/I79817857","display_name":"University of Guelph","ror":"https://ror.org/01r7awg59","country_code":"CA","type":"education","lineage":["https://openalex.org/I79817857"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"D. Banerji","raw_affiliation_strings":["Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computing and Information Science, University of Guelph, Guelph, ON, Canada","institution_ids":["https://openalex.org/I79817857"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020431979","display_name":"Alec Morton","orcid":"https://orcid.org/0000-0003-3803-8517"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"A. Morton","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017375445","display_name":"Mario Ventresca","orcid":"https://orcid.org/0000-0002-1246-297X"},"institutions":[{"id":"https://openalex.org/I151746483","display_name":"University of Waterloo","ror":"https://ror.org/01aff2v68","country_code":"CA","type":"education","lineage":["https://openalex.org/I151746483"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Ventresca","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada","institution_ids":["https://openalex.org/I151746483"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17012218,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"64","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8587706089019775},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6222679018974304},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.535695493221283},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4971325695514679},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.4740038812160492},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.4557071328163147},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.45505696535110474},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.42390140891075134},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.423869252204895},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4105024039745331},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.4056237041950226},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27189087867736816},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07687944173812866}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8587706089019775},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6222679018974304},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.535695493221283},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4971325695514679},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.4740038812160492},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.4557071328163147},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.45505696535110474},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.42390140891075134},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.423869252204895},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4105024039745331},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.4056237041950226},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27189087867736816},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07687944173812866}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cec.2006.1688291","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2006.1688291","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Conference on Evolutionary Computation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W405397024","https://openalex.org/W1581807583","https://openalex.org/W1985672179","https://openalex.org/W2011039300","https://openalex.org/W2025451108","https://openalex.org/W2036480385","https://openalex.org/W2105560756","https://openalex.org/W2121477346","https://openalex.org/W2148807560","https://openalex.org/W4237624134","https://openalex.org/W6635002728"],"related_works":["https://openalex.org/W4238754064","https://openalex.org/W2155373950","https://openalex.org/W2354036839","https://openalex.org/W2138825797","https://openalex.org/W2044064773","https://openalex.org/W4243618206","https://openalex.org/W4242495027","https://openalex.org/W4388838049","https://openalex.org/W4393076761","https://openalex.org/W2136268150"],"abstract_inverted_index":{"To":[0],"increase":[1],"memory":[2,20,26,34,93,143],"bandwidth,":[3],"many":[4],"programmable":[5],"Digital":[6],"Signal":[7],"Processors":[8],"(DSPs)":[9],"employ":[10],"two":[11],"on-chip":[12],"data":[13,25,79,106],"memories.":[14,82,124],"This":[15],"architectural":[16],"feature":[17],"supports":[18],"higher":[19],"bandwidth":[21],"by":[22],"allowing":[23],"multiple":[24],"accesses":[27],"to":[28,48,80,103,115,134,153],"occur":[29],"in":[30,44,92,122,139,148,155],"parallel.":[31],"Exploiting":[32],"dual":[33],"banks,":[35],"however,":[36],"is":[37,46,85,101,132],"a":[38,69,74,96,116,136,146],"challenging":[39],"problem":[40],"for":[41,77],"compilers.":[42],"This,":[43],"part,":[45],"due":[47],"the":[49,130,140,149,156],"instruction-level":[50],"parallelism,":[51],"small":[52],"numbers":[53],"of":[54,61,142,151,159],"registers,":[55],"and":[56,87,145,167],"highly":[57],"specialized":[58],"register":[59],"capabilities":[60],"most":[62],"DSPs.":[63],"In":[64],"this":[65],"paper,":[66],"we":[67],"present":[68],"new":[70],"methodology":[71],"based":[72],"on":[73],"genetic":[75],"algorithm":[76],"assigning":[78],"dual-bank":[81],"Our":[83,125],"approach":[84],"global,":[86],"integrates":[88],"several":[89],"important":[90],"issues":[91],"assignment":[94,114],"within":[95],"single":[97],"model.":[98],"Special":[99],"effort":[100],"made":[102],"identify":[104],"those":[105],"objects":[107],"that":[108,129],"could":[109],"potentially":[110],"benefit":[111],"from":[112],"an":[113],"specific":[117],"memory,":[118],"or":[119],"perhaps":[120],"duplication":[121],"both":[123],"computational":[126],"results":[127],"show":[128],"GA":[131],"able":[133],"achieve":[135],"54%":[137],"reduction":[138,147],"number":[141,158],"cycles":[144,160],"range":[150],"7%":[152],"42%":[154],"total":[157],"when":[161],"tested":[162],"with":[163],"well-known":[164],"DSP":[165],"kernels":[166],"applications.":[168]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}