{"id":"https://openalex.org/W1521496417","doi":"https://doi.org/10.1109/cec.2005.1554876","title":"Performance Driven Placement Technique based on Collaboration of Software and Hardware","display_name":"Performance Driven Placement Technique based on Collaboration of Software and Hardware","publication_year":2005,"publication_date":"2005-12-13","ids":{"openalex":"https://openalex.org/W1521496417","doi":"https://doi.org/10.1109/cec.2005.1554876","mag":"1521496417"},"language":"en","primary_location":{"id":"doi:10.1109/cec.2005.1554876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2005.1554876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE Congress on Evolutionary Computation","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048821605","display_name":"Masayuki Yoshikawa","orcid":"https://orcid.org/0000-0003-3106-3277"},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"M. Yoshikawa","raw_affiliation_strings":["Department of VLSI System Design, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of VLSI Syst. Design, Ritsumeikan Univ., Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of VLSI System Design, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of VLSI Syst. Design, Ritsumeikan Univ., Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110223979","display_name":"Hidekazu Terai","orcid":null},"institutions":[{"id":"https://openalex.org/I135768898","display_name":"Ritsumeikan University","ror":"https://ror.org/0197nmd03","country_code":"JP","type":"education","lineage":["https://openalex.org/I135768898","https://openalex.org/I4390039241"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Terai","raw_affiliation_strings":["Department of VLSI System Design, Ritsumeikan University, Kusatsu, Shiga, Japan","Dept. of VLSI Syst. Design, Ritsumeikan Univ., Shiga, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of VLSI System Design, Ritsumeikan University, Kusatsu, Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]},{"raw_affiliation_string":"Dept. of VLSI Syst. Design, Ritsumeikan Univ., Shiga, Japan","institution_ids":["https://openalex.org/I135768898"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.04620915,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"2","issue":null,"first_page":"1570","last_page":"1575"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7085561752319336},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5651921033859253},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5368478894233704},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5101590752601624},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5067363381385803},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4866364896297455},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.4815426468849182},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.46047109365463257},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.4367721974849701},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.38998091220855713},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3789956271648407},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.34771859645843506},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17517539858818054},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09886619448661804}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7085561752319336},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5651921033859253},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5368478894233704},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5101590752601624},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5067363381385803},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4866364896297455},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.4815426468849182},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.46047109365463257},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.4367721974849701},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.38998091220855713},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3789956271648407},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.34771859645843506},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17517539858818054},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09886619448661804},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cec.2005.1554876","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cec.2005.1554876","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2005 IEEE Congress on Evolutionary Computation","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8500000238418579,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1483231892","https://openalex.org/W1659842140","https://openalex.org/W1947575180","https://openalex.org/W1984588379","https://openalex.org/W2086716529","https://openalex.org/W2152150600","https://openalex.org/W2463573651","https://openalex.org/W6628989480","https://openalex.org/W6640606685","https://openalex.org/W6682679816","https://openalex.org/W6719578896"],"related_works":["https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W4249035840","https://openalex.org/W2766970861","https://openalex.org/W2018755015","https://openalex.org/W2065289416","https://openalex.org/W2017236304","https://openalex.org/W2115579119","https://openalex.org/W2136854845","https://openalex.org/W4382130817"],"abstract_inverted_index":{"Deep-sub-micron":[0],"(DSM)":[1],"technology":[2],"of":[3,11,40,89],"0.18":[4],"microns":[5],"and":[6,34,77,91],"below":[7],"enable":[8],"the":[9,97],"integration":[10],"logical":[12],"circuits":[13],"having":[14],"more":[15],"than":[16],"10":[17],"million":[18],"gates.":[19],"In":[20],"such":[21],"a":[22,46,59,83],"DSM":[23],"technology,":[24],"it":[25],"is":[26],"important":[27],"to":[28,95],"optimize":[29],"timing":[30],"constraint,":[31],"power":[32,78],"consumption":[33],"chip":[35,73],"area":[36],"at":[37],"initial":[38],"phase":[39],"layout":[41],"design.":[42],"This":[43],"paper":[44],"discusses":[45],"novel":[47,84],"performance-driven":[48],"placement":[49],"technique.":[50],"The":[51],"proposed":[52],"algorithm":[53],"based":[54,86],"on":[55,87],"genetic":[56],"algorithms":[57],"has":[58],"two-level":[60],"hierarchical":[61],"structure.":[62],"For":[63],"selection":[64],"control,":[65],"new":[66],"objective":[67],"functions":[68],"are":[69],"introduced":[70,82],"for":[71],"improving":[72],"area,":[74],"interconnect":[75],"delay":[76],"consumption.":[79],"Moreover,":[80],"we":[81],"approach":[85],"collaboration":[88],"software":[90],"hardware":[92],"in":[93],"order":[94],"reduce":[96],"run":[98],"time.":[99],"Experimental":[100],"result":[101],"shows":[102],"improvement":[103],"comparison":[104],"with":[105],"commercial":[106],"EDA":[107],"tool.":[108]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
