{"id":"https://openalex.org/W4366259362","doi":"https://doi.org/10.1109/ccwc57344.2023.10099370","title":"Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology","display_name":"Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology","publication_year":2023,"publication_date":"2023-03-08","ids":{"openalex":"https://openalex.org/W4366259362","doi":"https://doi.org/10.1109/ccwc57344.2023.10099370"},"language":"en","primary_location":{"id":"doi:10.1109/ccwc57344.2023.10099370","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccwc57344.2023.10099370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046137939","display_name":"Umme Hani Irin","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144275","display_name":"Dhaka University of Engineering & Technology","ror":"https://ror.org/03qxvyy35","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210144275"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Umme Hani Irin","raw_affiliation_strings":["Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","institution_ids":["https://openalex.org/I4210144275"]},{"raw_affiliation_string":"Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062893052","display_name":"Sajib Barua","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144275","display_name":"Dhaka University of Engineering & Technology","ror":"https://ror.org/03qxvyy35","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210144275"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Sajib Barua","raw_affiliation_strings":["Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","institution_ids":["https://openalex.org/I4210144275"]},{"raw_affiliation_string":"Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036549664","display_name":"Md Minhajul Azmir","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144275","display_name":"Dhaka University of Engineering & Technology","ror":"https://ror.org/03qxvyy35","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210144275"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Md Minhajul Azmir","raw_affiliation_strings":["Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","institution_ids":["https://openalex.org/I4210144275"]},{"raw_affiliation_string":"Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028853076","display_name":"Tasnuva Hassan","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144275","display_name":"Dhaka University of Engineering & Technology","ror":"https://ror.org/03qxvyy35","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210144275"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Tasnuva Hassan","raw_affiliation_strings":["Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","institution_ids":["https://openalex.org/I4210144275"]},{"raw_affiliation_string":"Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5013579132","display_name":"Dewan Mohammed","orcid":null},"institutions":[{"id":"https://openalex.org/I4210144275","display_name":"Dhaka University of Engineering & Technology","ror":"https://ror.org/03qxvyy35","country_code":"BD","type":"education","lineage":["https://openalex.org/I4210144275"]}],"countries":["BD"],"is_corresponding":false,"raw_author_name":"Dewan Mohammed","raw_affiliation_strings":["Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Ulkasemi Private Limited,Circuit and System Design Department,Dhaka,Bangladesh","institution_ids":["https://openalex.org/I4210144275"]},{"raw_affiliation_string":"Circuit and System Design Department, Ulkasemi Private Limited, Dhaka, Bangladesh","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210144275"],"apc_list":null,"apc_paid":null,"fwci":0.3637,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.57188937,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"0928","last_page":"0932"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8351330757141113},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6021575331687927},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.54376220703125},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5425825715065002},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5177011489868164},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5029763579368591},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.42859935760498047},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4124058187007904},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3907087445259094},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3670668601989746},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30559778213500977},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.27266430854797363},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19833135604858398},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1283724308013916}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8351330757141113},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6021575331687927},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.54376220703125},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5425825715065002},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5177011489868164},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5029763579368591},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.42859935760498047},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4124058187007904},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3907087445259094},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3670668601989746},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30559778213500977},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.27266430854797363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19833135604858398},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1283724308013916},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ccwc57344.2023.10099370","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccwc57344.2023.10099370","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2023 IEEE 13th Annual Computing and Communication Workshop and Conference (CCWC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8500000238418579,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1759929813","https://openalex.org/W1977334639","https://openalex.org/W2101328080","https://openalex.org/W2108470049","https://openalex.org/W2745140408","https://openalex.org/W2756848510","https://openalex.org/W4285503659"],"related_works":["https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W4293253840","https://openalex.org/W4378977321","https://openalex.org/W2967161359","https://openalex.org/W3211992815","https://openalex.org/W1976168335","https://openalex.org/W4241238243"],"abstract_inverted_index":{"This":[0],"paper":[1],"gives":[2],"an":[3],"overview":[4],"of":[5,70,153,168,172],"SRAM":[6,22,59,71,173],"design":[7,26],"requirements":[8],"and":[9,24,90,111,140,155],"optimization":[10],"methodologies":[11],"for":[12,76,88],"different":[13,21,58,68,170],"threshold":[14,32,53,78],"voltage":[15,33],"devices.":[16],"We":[17,46],"look":[18],"into":[19],"how":[20,57],"read":[23,89,154],"write":[25,91,156],"options":[27],"are":[28,61,74,98,149],"impacted":[29,62],"by":[30,42,63],"the":[31,82,166],"(V":[34],"<inf":[35,133,142],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[36,134,143],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">t</inf>":[37,135,144],")":[38],"changes":[39],"brought":[40],"on":[41],"process-voltage-temperature":[43],"(PVT)":[44],"variations.":[45],"investigated":[47],"several":[48],"approaches":[49],"to":[50,80,116],"achieve":[51],"reliable":[52],"functioning.":[54],"Additionally":[55],"emphasized":[56],"designs":[60],"process":[64],"modifications.":[65],"Here,":[66],"nine":[67,169],"types":[69],"bit":[72,84],"cells":[73],"analyzed":[75],"various":[77],"parameters":[79],"provide":[81],"optimal":[83],"cell":[85],"selection.":[86],"Performance":[87],"operations":[92],"as":[93,95,158,160],"well":[94,159],"power":[96,161],"consumption":[97],"compared":[99],"between":[100],"these":[101,118],"architectures.":[102],"All":[103],"simulations":[104],"were":[105],"performed":[106],"using":[107],"12nm":[108],"CMOS":[109],"technology,":[110],"Cadence":[112],"Tool":[113],"was":[114],"used":[115],"develop":[117],"designs.":[119],"To":[120],"reduce":[121],"leakage":[122],"current":[123],"without":[124],"compromising":[125],"performance,":[126],"it":[127],"has":[128],"been":[129],"observed":[130],"that":[131],"higher-V":[132],"devices":[136,145],"in":[137,146],"cross-coupled":[138],"latches":[139],"lower-V":[141],"access":[147],"transistors":[148],"favored.":[150],"In":[151],"terms":[152],"performance":[157,167],"consumption,":[162],"this":[163],"article":[164],"analyzes":[165],"kinds":[171],"bit-cells.":[174]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
