{"id":"https://openalex.org/W3210378525","doi":"https://doi.org/10.1109/ccece53047.2021.9569176","title":"Implementing Multistage Interconnection Networks on FPGA Using Chisel Language","display_name":"Implementing Multistage Interconnection Networks on FPGA Using Chisel Language","publication_year":2021,"publication_date":"2021-09-12","ids":{"openalex":"https://openalex.org/W3210378525","doi":"https://doi.org/10.1109/ccece53047.2021.9569176","mag":"3210378525"},"language":"en","primary_location":{"id":"doi:10.1109/ccece53047.2021.9569176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece53047.2021.9569176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023894041","display_name":"Andy Gallay","orcid":null},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Andy Gallay","raw_affiliation_strings":["Polytechnique Montr&#x00E9;al,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada"],"affiliations":[{"raw_affiliation_string":"Polytechnique Montr&#x00E9;al,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada","institution_ids":["https://openalex.org/I45683168"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065622787","display_name":"Tarek Ould\u2010Bachir","orcid":"https://orcid.org/0000-0002-9000-5467"},"institutions":[{"id":"https://openalex.org/I45683168","display_name":"Polytechnique Montr\u00e9al","ror":"https://ror.org/05f8d4e86","country_code":"CA","type":"education","lineage":["https://openalex.org/I45683168"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tarek Ould-Bachir","raw_affiliation_strings":["Polytechnique Montr&#x00E9;al,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada"],"affiliations":[{"raw_affiliation_string":"Polytechnique Montr&#x00E9;al,MOTCE Laboratory,Department of Computer Engineering,Montreal,PQ,Canada","institution_ids":["https://openalex.org/I45683168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5023894041"],"corresponding_institution_ids":["https://openalex.org/I45683168"],"apc_list":null,"apc_paid":null,"fwci":0.2346,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.51834721,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"c 29","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chisel","display_name":"Chisel","score":0.9270075559616089},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7704235315322876},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7413091063499451},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7240939736366272},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7122771739959717},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5094416737556458},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4981865882873535},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4431129992008209},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41330140829086304},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4054921865463257},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.39334771037101746},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.18081486225128174},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12488731741905212},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12239712476730347}],"concepts":[{"id":"https://openalex.org/C2775962983","wikidata":"https://www.wikidata.org/wiki/Q474188","display_name":"Chisel","level":2,"score":0.9270075559616089},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7704235315322876},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7413091063499451},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7240939736366272},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7122771739959717},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5094416737556458},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4981865882873535},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4431129992008209},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41330140829086304},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4054921865463257},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.39334771037101746},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.18081486225128174},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12488731741905212},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12239712476730347},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ccece53047.2021.9569176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece53047.2021.9569176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"},{"id":"pmh:oai:publications.polymtl.ca:49869","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/49869/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1983394510","https://openalex.org/W2044548351","https://openalex.org/W2100720925","https://openalex.org/W2134484974","https://openalex.org/W2160566592","https://openalex.org/W2166029537","https://openalex.org/W2497426795","https://openalex.org/W2771610171","https://openalex.org/W2907520127","https://openalex.org/W2979350050","https://openalex.org/W3000531743","https://openalex.org/W3134635013","https://openalex.org/W4240110784","https://openalex.org/W4240172596","https://openalex.org/W6772843964","https://openalex.org/W6791856793","https://openalex.org/W7071628024"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W2911649771","https://openalex.org/W2169179842","https://openalex.org/W2148697719","https://openalex.org/W2070083638"],"abstract_inverted_index":{"This":[0],"paper":[1,17,36,48],"discusses":[2,18],"the":[3,6,16,19,38,67,97],"utilization":[4],"of":[5,21,69],"highly":[7],"parametrizable":[8],"Chisel":[9,58,79],"language":[10],"for":[11],"FPGA":[12,28],"designs.":[13],"More":[14],"specifically,":[15],"implementation":[20],"multistage":[22],"interconnection":[23],"networks":[24],"(MINs)":[25],"on":[26],"an":[27],"using":[29],"Chisel.":[30],"The":[31,47],"MIN":[32],"considered":[33],"in":[34,72,83],"this":[35],"uses":[37],"well-known":[39],"butterfly":[40],"topology":[41],"and":[42,55,65,86,100],"a":[43,70,93,101],"latency-insensitive":[44],"design":[45,71],"approach.":[46],"compares":[49],"Chisel's":[50,88],"performance":[51],"against":[52],"handcrafted":[53],"VHDL,":[54],"demonstrates":[56],"that":[57,78],"simulation":[59],"capabilities":[60,91],"allows":[61],"one":[62],"to":[63,96],"explore":[64],"study":[66],"behavior":[68],"various":[73],"situations.":[74],"Our":[75],"findings":[76],"show":[77],"performs":[80],"very":[81],"well":[82],"both":[84],"space":[85],"speed.":[87],"powerful":[89],"testing":[90],"revealed":[92],"limitation":[94],"inherent":[95],"MIN's":[98],"architecture,":[99],"cost":[102],"effective":[103],"solution":[104],"is":[105],"proposed.":[106]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
