{"id":"https://openalex.org/W2979921829","doi":"https://doi.org/10.1109/ccece.2019.8861762","title":"Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors","display_name":"Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors","publication_year":2019,"publication_date":"2019-05-05","ids":{"openalex":"https://openalex.org/W2979921829","doi":"https://doi.org/10.1109/ccece.2019.8861762","mag":"2979921829"},"language":"en","primary_location":{"id":"doi:10.1109/ccece.2019.8861762","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2019.8861762","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029381714","display_name":"Furat Al-Obaidy","orcid":"https://orcid.org/0000-0002-3876-3746"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Furat Al-Obaidy","raw_affiliation_strings":["Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041995126","display_name":"Arghavan Asad","orcid":"https://orcid.org/0000-0001-9254-9479"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Arghavan Asad","raw_affiliation_strings":["Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103283614","display_name":"Farah Mohammadi","orcid":"https://orcid.org/0009-0008-9947-3209"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Farah Mohammadi","raw_affiliation_strings":["Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical, Computer, and Biomedical Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I530967"],"apc_list":null,"apc_paid":null,"fwci":0.8628,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.693971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"20","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7800862789154053},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6838276386260986},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6638873219490051},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5596957206726074},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.5579782128334045},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5302044153213501},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5113920569419861},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.4673213064670563},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.462560772895813},{"id":"https://openalex.org/keywords/power-management","display_name":"Power management","score":0.42052245140075684},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42012324929237366},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39573222398757935},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.3635264039039612},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.31920552253723145},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.17773601412773132}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7800862789154053},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6838276386260986},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6638873219490051},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5596957206726074},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.5579782128334045},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5302044153213501},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5113920569419861},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.4673213064670563},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.462560772895813},{"id":"https://openalex.org/C2778774385","wikidata":"https://www.wikidata.org/wiki/Q4437810","display_name":"Power management","level":3,"score":0.42052245140075684},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42012324929237366},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39573222398757935},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.3635264039039612},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.31920552253723145},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.17773601412773132},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ccece.2019.8861762","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2019.8861762","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8600000143051147,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W2001609213","https://openalex.org/W2006312753","https://openalex.org/W2033218087","https://openalex.org/W2084007230","https://openalex.org/W2104644701","https://openalex.org/W2142276919","https://openalex.org/W2147657366","https://openalex.org/W2170382128","https://openalex.org/W2263330644","https://openalex.org/W2610938932","https://openalex.org/W2746895391","https://openalex.org/W3147620158","https://openalex.org/W6651700774","https://openalex.org/W6675472944"],"related_works":["https://openalex.org/W2186949690","https://openalex.org/W2154109900","https://openalex.org/W3019064768","https://openalex.org/W3019683061","https://openalex.org/W3186016413","https://openalex.org/W3173293443","https://openalex.org/W4246122698","https://openalex.org/W1581731722","https://openalex.org/W2363750085","https://openalex.org/W3003475812"],"abstract_inverted_index":{"With":[0],"technology":[1,111],"scaling":[2],"and":[3,119,135],"increasing":[4],"parallelism":[5],"levels":[6],"of":[7,33,42,60,67],"new":[8,53,118],"embedded":[9],"applications,":[10],"multi-cores":[11],"in":[12,28,79,87],"chip-multiprocessors":[13],"(CMP)":[14],"has":[15,47],"been":[16,48],"increased.":[17],"In":[18],"this":[19,88],"context,":[20],"power":[21,72,131],"consumption":[22,132],"acts":[23],"a":[24,52,90],"critical":[25],"issue":[26],"concern":[27],"future":[29,37,99],"CMPs":[30,38],"with":[31,109],"restricted":[32],"battery":[34],"lifetime.":[35],"For":[36],"architecting,":[39],"3D":[40,65],"stacking":[41],"Last":[43],"Level":[44],"Cache":[45],"(LLC)":[46],"recently":[49],"introduced":[50],"as":[51],"methodology":[54],"to":[55,75,82],"combat":[56],"the":[57,64,114,127],"performance":[58],"challenges":[59],"2D":[61],"integration.":[62,84],"However,":[63],"design":[66],"LLCs":[68],"incurs":[69],"more":[70],"leakage":[71],"utilization":[73],"compared":[74],"conventional":[76],"cache":[77,96],"architectures":[78],"2Ds":[80],"due":[81],"dense":[83],"We":[85],"present":[86],"work":[89],"power-efficient":[91],"reconfigurable":[92],"hybrid":[93,103],"last":[94],"level":[95],"architecture":[97,104],"for":[98,116],"CMPs.":[100],"The":[101,122],"proposed":[102],"SRAM":[105],"memory":[106],"is":[107],"incorporated":[108],"STT-RAM":[110],"by":[112],"using":[113],"characteristics":[115],"both":[117],"traditional":[120],"technologies.":[121],"experimental":[123],"results":[124],"show":[125],"that":[126],"designed":[128],"method":[129],"minimizes":[130],"under":[133],"multi-programmed":[134],"multithreaded":[136],"applications.":[137]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":3}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}