{"id":"https://openalex.org/W1992759824","doi":"https://doi.org/10.1109/ccece.2013.6567802","title":"Spur analysis and reduction of edge combining DLL-based frequency multiplier","display_name":"Spur analysis and reduction of edge combining DLL-based frequency multiplier","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W1992759824","doi":"https://doi.org/10.1109/ccece.2013.6567802","mag":"1992759824"},"language":"en","primary_location":{"id":"doi:10.1109/ccece.2013.6567802","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2013.6567802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109976726","display_name":"Haizheng Guo","orcid":null},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Haizheng Guo","raw_affiliation_strings":["Carleton University, Ottawa, Canada"],"affiliations":[{"raw_affiliation_string":"Carleton University, Ottawa, Canada","institution_ids":["https://openalex.org/I67031392"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100626390","display_name":"Xinjie Wang","orcid":"https://orcid.org/0000-0002-9708-1518"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Xinjie Wang","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5109228020","display_name":"T. Kwa\u015bniewski","orcid":null},"institutions":[{"id":"https://openalex.org/I67031392","display_name":"Carleton University","ror":"https://ror.org/02qtvee93","country_code":"CA","type":"education","lineage":["https://openalex.org/I67031392"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tadeusz Kwasniewski","raw_affiliation_strings":["Carleton University, Ottawa, Canada"],"affiliations":[{"raw_affiliation_string":"Carleton University, Ottawa, Canada","institution_ids":["https://openalex.org/I67031392"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5109976726"],"corresponding_institution_ids":["https://openalex.org/I67031392"],"apc_list":null,"apc_paid":null,"fwci":0.7093,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.73477762,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"53","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-relationship","display_name":"Spurious relationship","score":0.821292519569397},{"id":"https://openalex.org/keywords/spur","display_name":"Spur","score":0.6394761800765991},{"id":"https://openalex.org/keywords/detector","display_name":"Detector","score":0.5713240504264832},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.5472792983055115},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5210427641868591},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.5133616328239441},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.49287986755371094},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.48387420177459717},{"id":"https://openalex.org/keywords/phase-frequency-detector","display_name":"Phase frequency detector","score":0.4499805271625519},{"id":"https://openalex.org/keywords/group-delay-and-phase-delay","display_name":"Group delay and phase delay","score":0.4381946623325348},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.43810591101646423},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3946583867073059},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.35681015253067017},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3428654372692108},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.3355787694454193},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.29285377264022827},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2340792417526245},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.23123306035995483},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.15651437640190125},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13958272337913513},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13482621312141418},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11067914962768555},{"id":"https://openalex.org/keywords/charge-pump","display_name":"Charge pump","score":0.07308980822563171},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.07292938232421875}],"concepts":[{"id":"https://openalex.org/C97256817","wikidata":"https://www.wikidata.org/wiki/Q1462316","display_name":"Spurious relationship","level":2,"score":0.821292519569397},{"id":"https://openalex.org/C2779821383","wikidata":"https://www.wikidata.org/wiki/Q7581537","display_name":"Spur","level":2,"score":0.6394761800765991},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.5713240504264832},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.5472792983055115},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5210427641868591},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.5133616328239441},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.49287986755371094},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.48387420177459717},{"id":"https://openalex.org/C2776158855","wikidata":"https://www.wikidata.org/wiki/Q2085341","display_name":"Phase frequency detector","level":5,"score":0.4499805271625519},{"id":"https://openalex.org/C123792056","wikidata":"https://www.wikidata.org/wiki/Q365988","display_name":"Group delay and phase delay","level":3,"score":0.4381946623325348},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.43810591101646423},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3946583867073059},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.35681015253067017},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3428654372692108},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.3355787694454193},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.29285377264022827},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2340792417526245},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.23123306035995483},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.15651437640190125},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13958272337913513},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13482621312141418},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11067914962768555},{"id":"https://openalex.org/C114825011","wikidata":"https://www.wikidata.org/wiki/Q440704","display_name":"Charge pump","level":4,"score":0.07308980822563171},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.07292938232421875},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ccece.2013.6567802","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2013.6567802","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1677884181","https://openalex.org/W1989743371","https://openalex.org/W2100869429","https://openalex.org/W2128446766","https://openalex.org/W2156456006","https://openalex.org/W2169190898","https://openalex.org/W2587442922","https://openalex.org/W6679066476"],"related_works":["https://openalex.org/W2508403993","https://openalex.org/W4385624389","https://openalex.org/W2147721077","https://openalex.org/W3177439118","https://openalex.org/W3189131640","https://openalex.org/W2137580552","https://openalex.org/W2119216036","https://openalex.org/W2366600570","https://openalex.org/W2060839350","https://openalex.org/W2103628070"],"abstract_inverted_index":{"A":[0,56],"detailed":[1],"study":[2],"of":[3,81,94,104],"reference":[4,22,105],"frequency":[5,14,71],"spurious":[6,65],"spectrum":[7],"components":[8,24,45],"in":[9,18,33],"edge-combining":[10],"delay-locked":[11],"loop":[12],"(DLL)-based":[13],"multipliers":[15],"is":[16,60],"presented":[17],"this":[19],"paper.":[20],"The":[21,98],"spur":[23,44],"caused":[25],"by":[26,89],"the":[27,34,43,64,68,78,87,91],"delay":[28,31,37,92,96],"mismatch":[29],"between":[30],"cells":[32],"voltage":[35],"controlled":[36],"line":[38],"(VCDL),":[39],"as":[40,42],"well":[41],"due":[46],"to":[47,62],"phase":[48],"detector":[49,76],"locking":[50],"error":[51,75,88],"are":[52],"analyzed":[53],"and":[54,84],"unified.":[55],"digital":[57],"calibration":[58],"method":[59],"proposed":[61],"lower":[63],"tone":[66],"for":[67,86],"DLL":[69],"based":[70],"multiplier":[72],"output.":[73],"An":[74],"compares":[77],"timing":[79],"difference":[80],"each":[82,95],"sub-period":[83],"compensates":[85],"adjusting":[90],"time":[93],"cell.":[97],"simulation":[99],"results":[100],"show":[101],"a":[102],"reduction":[103],"spur.":[106]},"counts_by_year":[{"year":2019,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}