{"id":"https://openalex.org/W2001344605","doi":"https://doi.org/10.1109/ccece.2013.6567789","title":"Gigabyte-scale alignment of biological sequences: A case study of IO bandwidth reconfiguration for FPGA acceleration","display_name":"Gigabyte-scale alignment of biological sequences: A case study of IO bandwidth reconfiguration for FPGA acceleration","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W2001344605","doi":"https://doi.org/10.1109/ccece.2013.6567789","mag":"2001344605"},"language":"en","primary_location":{"id":"doi:10.1109/ccece.2013.6567789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2013.6567789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045141981","display_name":"Theepan Moorthy","orcid":"https://orcid.org/0000-0002-5969-3791"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Theepan Moorthy","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of British Columbia, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of British Columbia, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111619748","display_name":"Jan M. Correa","orcid":null},"institutions":[{"id":"https://openalex.org/I150729083","display_name":"Universidade de Bras\u00edlia","ror":"https://ror.org/02xfp8v59","country_code":"BR","type":"education","lineage":["https://openalex.org/I150729083"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Jan M. Correa","raw_affiliation_strings":["Department of Computer Science, University of Brasilia","[Dept. of Computer Science, University of Bras\u00edlia, Bras\u00edlia, Brazil]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Brasilia","institution_ids":["https://openalex.org/I150729083"]},{"raw_affiliation_string":"[Dept. of Computer Science, University of Bras\u00edlia, Bras\u00edlia, Brazil]","institution_ids":["https://openalex.org/I150729083"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103175261","display_name":"Sathish Gopalakrishnan","orcid":"https://orcid.org/0000-0003-2959-4802"},"institutions":[{"id":"https://openalex.org/I141945490","display_name":"University of British Columbia","ror":"https://ror.org/03rmrcq20","country_code":"CA","type":"education","lineage":["https://openalex.org/I141945490"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Sathish Gopalakrishnan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, The University of British Columbia, Canada","Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, The University of British Columbia, Canada","institution_ids":["https://openalex.org/I141945490"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Univ. of British Columbia., Vancouver, BC, Canada","institution_ids":["https://openalex.org/I141945490"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9869999885559082,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9869999885559082,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9828000068664551,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10015","display_name":"Genomics and Phylogenetic Studies","score":0.9757999777793884,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8171610236167908},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7965437173843384},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.790573239326477},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7770093083381653},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.7574700117111206},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.5595429539680481},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5067494511604309},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3728744387626648},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3251255750656128},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3007289171218872},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.12463772296905518},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.08535856008529663}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8171610236167908},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7965437173843384},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.790573239326477},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7770093083381653},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.7574700117111206},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.5595429539680481},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5067494511604309},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3728744387626648},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3251255750656128},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3007289171218872},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.12463772296905518},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.08535856008529663},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ccece.2013.6567789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2013.6567789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 26th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6299999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1784358612","https://openalex.org/W2036295979","https://openalex.org/W2054388411","https://openalex.org/W2087064593","https://openalex.org/W2123472193","https://openalex.org/W2139377814","https://openalex.org/W2140350225","https://openalex.org/W2144316495","https://openalex.org/W2144597359","https://openalex.org/W2152983905","https://openalex.org/W2163391648","https://openalex.org/W2172119162","https://openalex.org/W2541397455","https://openalex.org/W3140730966","https://openalex.org/W6638042978"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"We":[0,22],"expose":[1],"the":[2,12,15,24,31,40,83,134],"implementation":[3,25],"challenges":[4],"to":[5,18,48,91,95,109,120,129],"sustaining":[6],"acceleration":[7],"speedups":[8],"on":[9,66],"FPGAs":[10],"as":[11,82,127],"size":[13],"of":[14,26,33,71,136],"data":[16,85,100],"set":[17,86],"be":[19,46,92],"processed":[20],"scales.":[21,87],"examine":[23],"an":[27],"FPGA":[28,116],"platform":[29],"for":[30,104],"processing":[32],"gigabyte":[34],"scale":[35],"biological":[36],"sequences,":[37],"and":[38,102],"illustrate":[39],"significant":[41],"design":[42,62],"changes":[43],"that":[44,58,64],"must":[45],"made":[47],"achieve":[49],"a":[50,107,114],"successful":[51],"implementation.":[52],"In":[53],"doing":[54],"so,":[55],"we":[56,112],"demonstrate":[57],"conventional":[59],"accelerator":[60],"architecture":[61],"choices":[63],"focus":[65],"throughput":[67,80,132],"speedup,":[68],"in":[69,133],"isolation":[70],"system":[72],"level":[73],"IO":[74,118],"bandwidth":[75,123],"feasibility,":[76],"cannot":[77],"sustain":[78],"their":[79],"levels":[81],"input":[84],"This":[88],"is":[89],"shown":[90],"primarily":[93],"due":[94],"currently":[96],"unavailable":[97],"high-bandwidth":[98],"large-scale":[99],"storage":[101,125],"retrieval":[103],"FPGAs.":[105],"As":[106],"solution":[108],"this":[110],"problem,":[111],"propose":[113],"general":[115],"based":[117],"infrastructure":[119],"utilize":[121],"high":[122],"hard-drive":[124],"options,":[126],"means":[128],"achieving":[130],"sustained":[131],"face":[135],"large":[137],"data.":[138]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
