{"id":"https://openalex.org/W2170504327","doi":"https://doi.org/10.1109/ccece.2011.6030497","title":"Reconfigurable logic based on tunable periodic characteristics of single-electron transistor","display_name":"Reconfigurable logic based on tunable periodic characteristics of single-electron transistor","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2170504327","doi":"https://doi.org/10.1109/ccece.2011.6030497","mag":"2170504327"},"language":"en","primary_location":{"id":"doi:10.1109/ccece.2011.6030497","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2011.6030497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059001985","display_name":"Bingcai Sui","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Bingcai Sui","raw_affiliation_strings":["PDL, School of Computer, National University of Defense Technology, Hunan, China"],"affiliations":[{"raw_affiliation_string":"PDL, School of Computer, National University of Defense Technology, Hunan, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067018873","display_name":"Liang Fang","orcid":"https://orcid.org/0000-0003-3498-3685"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Liang Fang","raw_affiliation_strings":["PDL, School of Computer, National University of Defense Technology, Hunan, China"],"affiliations":[{"raw_affiliation_string":"PDL, School of Computer, National University of Defense Technology, Hunan, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100405888","display_name":"Chao Zhang","orcid":"https://orcid.org/0000-0002-2817-0488"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chao Zhang","raw_affiliation_strings":["PDL, School of Computer, National University of Defense Technology, Hunan, China"],"affiliations":[{"raw_affiliation_string":"PDL, School of Computer, National University of Defense Technology, Hunan, China","institution_ids":["https://openalex.org/I170215575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059001985"],"corresponding_institution_ids":["https://openalex.org/I170215575"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.17782399,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"000485","last_page":"000488"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10382","display_name":"Quantum and electron transport phenomena","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10382","display_name":"Quantum and electron transport phenomena","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13531","display_name":"Surface and Thin Film Phenomena","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/3107","display_name":"Atomic and Molecular Physics, and Optics"},"field":{"id":"https://openalex.org/fields/31","display_name":"Physics and Astronomy"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10913","display_name":"Molecular Junctions and Nanostructures","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.7369968295097351},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.7039691805839539},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.693344235420227},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6878876090049744},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6466742157936096},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6140102744102478},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.6008241176605225},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5760750770568848},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5502193570137024},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5417173504829407},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5078235268592834},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4788001477718353},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.404304176568985},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.37678301334381104},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26728004217147827},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2107866108417511},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19804570078849792},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.19636857509613037},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07223621010780334}],"concepts":[{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.7369968295097351},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.7039691805839539},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.693344235420227},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6878876090049744},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6466742157936096},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6140102744102478},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.6008241176605225},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5760750770568848},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5502193570137024},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5417173504829407},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5078235268592834},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4788001477718353},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.404304176568985},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.37678301334381104},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26728004217147827},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2107866108417511},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19804570078849792},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.19636857509613037},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07223621010780334}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ccece.2011.6030497","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ccece.2011.6030497","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8700000047683716}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1602504737","https://openalex.org/W1929338932","https://openalex.org/W2036926171","https://openalex.org/W2127265436","https://openalex.org/W2140852740"],"related_works":["https://openalex.org/W3105918491","https://openalex.org/W2151236218","https://openalex.org/W2102777336","https://openalex.org/W4234601000","https://openalex.org/W2490069675","https://openalex.org/W2197466303","https://openalex.org/W2121969545","https://openalex.org/W2139569078","https://openalex.org/W2254425074","https://openalex.org/W2170504327"],"abstract_inverted_index":{"Single-electron":[0],"transistor":[1],"(SET),":[2],"the":[3,8,27,50,90],"most":[4],"promising":[5],"candidate":[6],"for":[7,105],"post-CMOS":[9],"era,":[10],"can":[11,58,92,102,114],"deliver":[12],"high":[13],"device":[14],"density":[15],"and":[16,54,101,123],"power":[17],"efficiency":[18],"at":[19],"reasonable":[20],"speed.":[21],"The":[22,85],"THmnW":[23,57,80,98],"logic":[24,36,81,99,107],"gate":[25,39],"is":[26,43,83],"basic":[28],"element":[29],"used":[30,94,116],"in":[31,45],"constructing":[32],"a":[33,66,74],"NULL":[34],"convention":[35],"(NCL)":[37],"field-programmable":[38],"array":[40],"(FPGA),":[41],"which":[42],"useful":[44,104],"embedded":[46],"systems.":[47],"We":[48],"investigate":[49],"tunability":[51],"of":[52,77],"SETs":[53],"find":[55],"that":[56,89],"be":[59,93,103,115],"implemented":[60,70],"with":[61],"SET":[62,72],"logic.":[63],"By":[64],"using":[65,71],"tunable":[67],"periodic":[68],"function":[69],"logic,":[73],"novel":[75],"method":[76,91,113],"flexibly":[78,96],"designing":[79,106],"gates":[82,100,108],"proposed.":[84],"simulation":[86],"results":[87],"show":[88],"to":[95,117],"design":[97,118],"based":[109],"on":[110],"SETs.":[111],"This":[112],"structures":[119],"such":[120],"as":[121],"FPGAs":[122],"programmable":[124],"architectures":[125],"more":[126],"efficiently.":[127]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
