{"id":"https://openalex.org/W4230327065","doi":"https://doi.org/10.1109/cases.2013.6662513","title":"CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors","display_name":"CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W4230327065","doi":"https://doi.org/10.1109/cases.2013.6662513"},"language":"en","primary_location":{"id":"doi:10.1109/cases.2013.6662513","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cases.2013.6662513","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041672444","display_name":"Vasileios Porpodas","orcid":null},"institutions":[{"id":"https://openalex.org/I98677209","display_name":"University of Edinburgh","ror":"https://ror.org/01nrxwf90","country_code":"GB","type":"education","lineage":["https://openalex.org/I98677209"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Vasileios Porpodas","raw_affiliation_strings":["School of Informatics, University of Edinburgh"],"affiliations":[{"raw_affiliation_string":"School of Informatics, University of Edinburgh","institution_ids":["https://openalex.org/I98677209"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5090902844","display_name":"Marcelo Cintra","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Marcelo Cintra","raw_affiliation_strings":["Sabbatical leave at Intel Labs"],"affiliations":[{"raw_affiliation_string":"Sabbatical leave at Intel Labs","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5041672444"],"corresponding_institution_ids":["https://openalex.org/I98677209"],"apc_list":null,"apc_paid":null,"fwci":0.3152,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.66056602,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.891800045967102},{"id":"https://openalex.org/keywords/very-long-instruction-word","display_name":"Very long instruction word","score":0.8451632261276245},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6976441144943237},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6190694570541382},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5904344320297241},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.568749189376831},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.561231255531311},{"id":"https://openalex.org/keywords/reuse","display_name":"Reuse","score":0.556729793548584},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.465376079082489},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3684680461883545},{"id":"https://openalex.org/keywords/fair-share-scheduling","display_name":"Fair-share scheduling","score":0.2883038818836212},{"id":"https://openalex.org/keywords/two-level-scheduling","display_name":"Two-level scheduling","score":0.21379125118255615},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11299148201942444},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11257484555244446}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.891800045967102},{"id":"https://openalex.org/C170595534","wikidata":"https://www.wikidata.org/wiki/Q249743","display_name":"Very long instruction word","level":2,"score":0.8451632261276245},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6976441144943237},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6190694570541382},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5904344320297241},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.568749189376831},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.561231255531311},{"id":"https://openalex.org/C206588197","wikidata":"https://www.wikidata.org/wiki/Q846574","display_name":"Reuse","level":2,"score":0.556729793548584},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.465376079082489},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3684680461883545},{"id":"https://openalex.org/C31689143","wikidata":"https://www.wikidata.org/wiki/Q733809","display_name":"Fair-share scheduling","level":3,"score":0.2883038818836212},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.21379125118255615},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11299148201942444},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11257484555244446},{"id":"https://openalex.org/C5119721","wikidata":"https://www.wikidata.org/wiki/Q220501","display_name":"Quality of service","level":2,"score":0.0},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cases.2013.6662513","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cases.2013.6662513","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.41999998688697815,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":35,"referenced_works":["https://openalex.org/W12207660","https://openalex.org/W105128281","https://openalex.org/W1608995421","https://openalex.org/W1966668827","https://openalex.org/W1977462696","https://openalex.org/W1979072566","https://openalex.org/W1986535055","https://openalex.org/W2034393996","https://openalex.org/W2037975285","https://openalex.org/W2040167141","https://openalex.org/W2054211050","https://openalex.org/W2063255488","https://openalex.org/W2084451631","https://openalex.org/W2087256755","https://openalex.org/W2105884870","https://openalex.org/W2114067856","https://openalex.org/W2116548071","https://openalex.org/W2129207930","https://openalex.org/W2129962996","https://openalex.org/W2138351227","https://openalex.org/W2142685136","https://openalex.org/W2143894108","https://openalex.org/W2147345262","https://openalex.org/W2157373341","https://openalex.org/W2165064225","https://openalex.org/W2172212694","https://openalex.org/W3147835733","https://openalex.org/W4239015185","https://openalex.org/W4242172296","https://openalex.org/W4242368470","https://openalex.org/W4246289115","https://openalex.org/W6604335647","https://openalex.org/W6644631221","https://openalex.org/W6684336322","https://openalex.org/W6793159789"],"related_works":["https://openalex.org/W2734211308","https://openalex.org/W1506210504","https://openalex.org/W2103250493","https://openalex.org/W2353958330","https://openalex.org/W2134136106","https://openalex.org/W4242411138","https://openalex.org/W89872709","https://openalex.org/W2372381897","https://openalex.org/W2105166755","https://openalex.org/W1566248920"],"abstract_inverted_index":{"Clustered":[0],"architectures":[1],"have":[2],"been":[3],"proposed":[4,88],"as":[5,39],"a":[6,59],"solution":[7],"to":[8,133],"the":[9,50,108,118,140,144],"scalability":[10],"problem":[11],"of":[12,131],"wide":[13],"ILP":[14],"processors.":[15],"VLIW":[16],"architectures,":[17,27],"being":[18,28],"wide-issue":[19],"by":[20,92],"design,":[21],"benefit":[22],"significantly":[23],"from":[24],"clustering.":[25],"Such":[26],"both":[29],"statically":[30],"scheduled":[31,48],"and":[32,77,101,110,114,135],"clustered,":[33],"require":[34,41],"specialized":[35],"code":[36,51,66,99],"generation":[37,67,100],"techniques,":[38],"they":[40],"explicit":[42],"Inter-Cluster":[43],"Copy":[44],"instructions":[45],"(ICCs)":[46],"be":[47],"in":[49,82,128],"stream.":[52],"In":[53],"this":[54],"work":[55],"we":[56],"propose":[57],"CAeSaR,":[58],"novel":[60],"instruction":[61,75,120],"scheduling":[62,76,121],"algorithm":[63,89],"that":[64],"improves":[65,90],"for":[68],"such":[69],"architectures.":[70],"It":[71],"combines":[72],"cluster":[73],"assignment,":[74],"inter-cluster":[78],"communication":[79],"reuse":[80],"all":[81],"one":[83],"single":[84],"unified":[85],"algorithm.":[86,122],"The":[87],"performance":[91],"any":[93],"phase-ordering":[94],"issues":[95],"among":[96],"these":[97],"three":[98],"optimization":[102],"steps.":[103],"We":[104],"evaluate":[105],"CAeSaR":[106],"on":[107,137],"MediabenchII":[109],"SPEC":[111],"CINT2000":[112],"benchmarks":[113],"compare":[115],"it":[116],"against":[117],"state-of-the-art":[119,142],"Our":[123],"results":[124],"show":[125],"an":[126],"improvement":[127],"execution":[129],"time":[130],"up":[132],"20.3%,":[134],"13.8%":[136],"average,":[138],"over":[139],"current":[141],"across":[143],"benchmarks.":[145]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
