{"id":"https://openalex.org/W2157713675","doi":"https://doi.org/10.1109/cadcg.2007.4407901","title":"Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching","display_name":"Transistor Level Timing Analysis Considering Multiple Inputs Simultaneous Switching","publication_year":2007,"publication_date":"2007-10-01","ids":{"openalex":"https://openalex.org/W2157713675","doi":"https://doi.org/10.1109/cadcg.2007.4407901","mag":"2157713675"},"language":"en","primary_location":{"id":"doi:10.1109/cadcg.2007.4407901","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cadcg.2007.4407901","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101926349","display_name":"Zhentao Li","orcid":"https://orcid.org/0000-0001-7178-033X"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhentao Li","raw_affiliation_strings":["School of Computer Science, National University of Defense Technology, Changsha, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100644317","display_name":"Shuming Chen","orcid":"https://orcid.org/0000-0003-4441-2202"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuming Chen","raw_affiliation_strings":["School of Computer Science, National University of Defense Technology, Changsha, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, National University of Defense Technology, Changsha, China","institution_ids":["https://openalex.org/I170215575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I170215575"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"315","last_page":"320"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.691874623298645},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6552431583404541},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6540434956550598},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6330627202987671},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.6210185289382935},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6146187782287598},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6060044169425964},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.5637093782424927},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5442339777946472},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5351181030273438},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5201214551925659},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.5118993520736694},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.4586837589740753},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3198549747467041},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20950287580490112},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20442146062850952},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.19804343581199646},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08804899454116821},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06336742639541626}],"concepts":[{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.691874623298645},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6552431583404541},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6540434956550598},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6330627202987671},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.6210185289382935},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6146187782287598},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6060044169425964},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.5637093782424927},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5442339777946472},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5351181030273438},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5201214551925659},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.5118993520736694},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.4586837589740753},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3198549747467041},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20950287580490112},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20442146062850952},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.19804343581199646},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08804899454116821},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06336742639541626},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/cadcg.2007.4407901","is_oa":false,"landing_page_url":"https://doi.org/10.1109/cadcg.2007.4407901","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2012336463","https://openalex.org/W2100272847","https://openalex.org/W2115296652","https://openalex.org/W2150382568","https://openalex.org/W2150985480","https://openalex.org/W2156360520","https://openalex.org/W2157955053","https://openalex.org/W2158636856","https://openalex.org/W4237437637","https://openalex.org/W6681800627","https://openalex.org/W6682268157","https://openalex.org/W6683553011"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W4229446324","https://openalex.org/W2158805860","https://openalex.org/W2110367374","https://openalex.org/W3151506308","https://openalex.org/W1986294008","https://openalex.org/W2345182073","https://openalex.org/W4281385583","https://openalex.org/W1947426333","https://openalex.org/W1500562608"],"abstract_inverted_index":{"To":[0],"overcome":[1],"the":[2,24,41,52],"problems":[3],"of":[4,26,75,98],"traditional":[5],"delay":[6,17,33,68],"models,":[7],"this":[8,48],"paper":[9],"uses":[10],"a":[11,36,80],"circuit":[12],"simulator":[13],"to":[14,39],"calculate":[15,40],"gate":[16,32,44,67],"in":[18],"static":[19,83],"timing":[20,84],"analysis.":[21],"We":[22],"analyzed":[23],"effect":[25],"multiple":[27],"inputs":[28],"simultaneous":[29],"switching(MISS)":[30],"on":[31,47,90],"and":[34,61],"proposed":[35],"MISS":[37],"model":[38,72],"worst":[42],"case":[43],"delay.":[45],"Based":[46],"model,":[49],"we":[50,78],"developed":[51],"test":[53],"waveform":[54],"generation":[55],"algorithms":[56],"for":[57],"complementary":[58],"CMOS":[59],"logic":[60],"pass":[62],"transistor":[63,76,81],"logic.":[64],"By":[65],"combining":[66],"simulation":[69],"with":[70,106],"functional":[71],"extraction":[73],"techniques":[74],"circuits,":[77],"implemented":[79],"level":[82],"analysis":[85],"tool":[86],"called":[87],"SpiceTime.":[88],"Results":[89],"ten":[91],"IS-CAS85":[92],"benchmark":[93],"circuits":[94],"indicated":[95],"that":[96],"modules":[97],"significant":[99],"size":[100],"can":[101],"be":[102],"verified":[103],"by":[104],"SpiceTime":[105],"high":[107],"precisions.":[108]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}