{"id":"https://openalex.org/W2164843628","doi":"https://doi.org/10.1109/bmas.2009.5338883","title":"Fast and waveform independent characterization of current source models","display_name":"Fast and waveform independent characterization of current source models","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2164843628","doi":"https://doi.org/10.1109/bmas.2009.5338883","mag":"2164843628"},"language":"en","primary_location":{"id":"doi:10.1109/bmas.2009.5338883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/bmas.2009.5338883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Behavioral Modeling and Simulation Workshop","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087816487","display_name":"Christoph Knoth","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Christoph Knoth","raw_affiliation_strings":["Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067335661","display_name":"Veit B. Kleeberger","orcid":"https://orcid.org/0000-0003-4685-2439"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Veit B. Kleeberger","raw_affiliation_strings":["Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070243037","display_name":"Petra Nordholz","orcid":null},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Petra Nordholz","raw_affiliation_strings":["Infineon Technologies, Neubiberg, Germany"],"affiliations":[{"raw_affiliation_string":"Infineon Technologies, Neubiberg, Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5017567485","display_name":"Ulf Schlichtmann","orcid":"https://orcid.org/0000-0003-4431-7619"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ulf Schlichtmann","raw_affiliation_strings":["Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany"],"affiliations":[{"raw_affiliation_string":"Institute for Electronic Design Automation Technische, Universit\u00e4t Munchen, Germany","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5087816487"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":1.4954,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.84408552,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"95"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8041542768478394},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.791990339756012},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.741613507270813},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7196654081344604},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.6342577338218689},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.5706173777580261},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5408445596694946},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.49820756912231445},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.47779780626296997},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4388091564178467},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.43490070104599},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3257614076137543},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.302634596824646},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2758719325065613},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2070828676223755},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17644545435905457},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13290497660636902}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8041542768478394},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.791990339756012},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.741613507270813},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7196654081344604},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.6342577338218689},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.5706173777580261},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5408445596694946},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.49820756912231445},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.47779780626296997},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4388091564178467},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.43490070104599},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3257614076137543},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.302634596824646},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2758719325065613},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2070828676223755},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17644545435905457},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13290497660636902},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/bmas.2009.5338883","is_oa":false,"landing_page_url":"https://doi.org/10.1109/bmas.2009.5338883","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE Behavioral Modeling and Simulation Workshop","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W600310561","https://openalex.org/W1547254974","https://openalex.org/W1555121108","https://openalex.org/W2005624023","https://openalex.org/W2097913753","https://openalex.org/W2106251971","https://openalex.org/W2110029214","https://openalex.org/W2112918184","https://openalex.org/W2133268384","https://openalex.org/W2142202849","https://openalex.org/W2153387509","https://openalex.org/W2154680820","https://openalex.org/W3140936136","https://openalex.org/W3148971007","https://openalex.org/W4237823089","https://openalex.org/W6676633326","https://openalex.org/W6680739566"],"related_works":["https://openalex.org/W4380987687","https://openalex.org/W1962246972","https://openalex.org/W2107551409","https://openalex.org/W4249541960","https://openalex.org/W4312335373","https://openalex.org/W3136219993","https://openalex.org/W4249292140","https://openalex.org/W2077986289","https://openalex.org/W4251160711","https://openalex.org/W2014225467"],"abstract_inverted_index":{"A":[0],"fast":[1],"characterization":[2,66],"method":[3],"for":[4,36,91],"current":[5],"source":[6],"models":[7],"(CSM)":[8],"is":[9,51,58,67],"proposed.":[10],"It":[11],"analyses":[12],"the":[13,30,37,54],"given":[14],"transistor":[15],"netlist":[16],"of":[17,39,70,76,101,106,120],"CMOS":[18],"logic":[19,44],"cells":[20],"to":[21,53,60],"determine":[22],"both":[23],"static":[24],"and":[25],"dynamic":[26],"CSM":[27],"parameters":[28],"in":[29,42,96],"same":[31],"DC":[32],"simulation.":[33],"To":[34],"account":[35],"influence":[38],"parasitic":[40],"elements":[41],"large":[43],"cells,":[45],"an":[46],"additional":[47],"low":[48],"pass":[49],"filter":[50],"inserted":[52],"CSMs.":[55],"AC":[56],"analysis":[57,100],"employed":[59],"efficiently":[61],"define":[62],"its":[63],"parameters.":[64],"The":[65],"therefore":[68],"independent":[69],"user":[71],"specified":[72],"input":[73,93],"waveforms.":[74,94],"CSMs":[75],"industrial":[77],"gates":[78],"have":[79,108],"been":[80,109],"integrated":[81],"into":[82],"a":[83,118],"standard":[84],"SPICE":[85],"simulator,":[86],"showing":[87],"high":[88],"accuracy":[89],"also":[90],"noisy":[92],"Used":[95],"path":[97],"based":[98],"timing":[99],"ISCAS85":[102],"circuits,":[103],"average":[104],"errors":[105],"3%":[107],"observed":[110],"while":[111],"simulation":[112],"times":[113],"could":[114],"be":[115],"reduced":[116],"by":[117],"factor":[119],"100.":[121]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
