{"id":"https://openalex.org/W4408443107","doi":"https://doi.org/10.1109/ats64447.2024.10915527","title":"Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs","display_name":"Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs","publication_year":2024,"publication_date":"2024-12-17","ids":{"openalex":"https://openalex.org/W4408443107","doi":"https://doi.org/10.1109/ats64447.2024.10915527"},"language":"en","primary_location":{"id":"doi:10.1109/ats64447.2024.10915527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats64447.2024.10915527","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 33rd Asian Test Symposium (ATS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055779873","display_name":"Venkata Sreekanth Balijabudda","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Venkata Sreekanth Balijabudda","raw_affiliation_strings":["IIT Kharagpur,Adv. Tech. Develop. Cent,Kharagpur,West Bengal,India,721302"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur,Adv. Tech. Develop. Cent,Kharagpur,West Bengal,India,721302","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003667123","display_name":"Indrajit Chakrabarti","orcid":"https://orcid.org/0000-0003-4744-2132"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Indrajit Chakrabarti","raw_affiliation_strings":["IIT Kharagpur,Dept. of Electr. and Elec. Comm. Engg,Kharagpur,West Bengal,India,721302"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur,Dept. of Electr. and Elec. Comm. Engg,Kharagpur,West Bengal,India,721302","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049426113","display_name":"Rajat Subhra Chakraborty","orcid":"https://orcid.org/0000-0003-3588-163X"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajat Subhra Chakraborty","raw_affiliation_strings":["IIT Kharagpur,Dept. of Comp. Sc. and Engg,Kharagpur,West Bengal,India,721302"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IIT Kharagpur,Dept. of Comp. Sc. and Engg,Kharagpur,West Bengal,India,721302","institution_ids":["https://openalex.org/I145894827"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.443,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.66964729,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/arbiter","display_name":"Arbiter","score":0.970914900302887},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8197524547576904},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6100374460220337},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5570258498191833},{"id":"https://openalex.org/keywords/characterization","display_name":"Characterization (materials science)","score":0.5508683323860168},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4871346652507782},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2849196195602417},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.08395910263061523},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.07920905947685242}],"concepts":[{"id":"https://openalex.org/C2779971761","wikidata":"https://www.wikidata.org/wiki/Q629872","display_name":"Arbiter","level":2,"score":0.970914900302887},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8197524547576904},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6100374460220337},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5570258498191833},{"id":"https://openalex.org/C2780841128","wikidata":"https://www.wikidata.org/wiki/Q5073781","display_name":"Characterization (materials science)","level":2,"score":0.5508683323860168},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4871346652507782},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2849196195602417},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.08395910263061523},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.07920905947685242}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ats64447.2024.10915527","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ats64447.2024.10915527","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2024 IEEE 33rd Asian Test Symposium (ATS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1989091271","https://openalex.org/W2014457808","https://openalex.org/W2070196900","https://openalex.org/W2080284304","https://openalex.org/W2084459802","https://openalex.org/W2088455835","https://openalex.org/W2104401100","https://openalex.org/W2165642710","https://openalex.org/W2908600804","https://openalex.org/W2949389056","https://openalex.org/W2971643716","https://openalex.org/W3091854260","https://openalex.org/W4285303121","https://openalex.org/W6676995458","https://openalex.org/W6678473589"],"related_works":["https://openalex.org/W2884038052","https://openalex.org/W2982348224","https://openalex.org/W2135481122","https://openalex.org/W2096844293","https://openalex.org/W2363944576","https://openalex.org/W2351041855","https://openalex.org/W2570254841","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"An":[0],"Arbiter":[1],"PUF":[2],"(APUF)":[3],"is":[4,41,71,74,131,142,185],"a":[5,36,62,172,182],"useful":[6],"hardware":[7],"security":[8,183],"primitive.":[9],"However,":[10],"FPGA-based":[11],"design":[12,141],"and":[13,58,73,85,88,108,122,159,168,181],"implementation":[14,60],"of":[15,21,50,83,91,117,166,174,190],"APUF":[16,39,101],"circuits":[17],"with":[18,155],"superior":[19],"values":[20,49,116],"quality":[22,51],"metrics":[23,52],"have":[24,34,94],"proven":[25],"to":[26,47,145,149],"be":[27,146],"extremely":[28],"challenging.":[29],"In":[30],"this":[31],"work,":[32],"we":[33],"designed":[35],"novel":[37],"64-bit":[38],"which":[40],"\"robust-by-construction\",":[42],"i.e.,":[43],"it":[44],"has":[45],"close":[46],"ideal":[48],"when":[53],"implemented.":[54],"The":[55,81,140],"circuit":[56],"structure":[57],"methodical":[59],"on":[61,76,133,171],"Xilinx":[63],"FPGA":[64],"platform":[65],"ensure":[66],"that":[67],"the":[68,89,134,191],"response":[69],"bit":[70],"unbiased,":[72],"dependent":[75],"intrinsic":[77],"process":[78],"variation":[79],"alone.":[80],"effect":[82],"placement":[84],"routing":[86],"tools":[87],"choice":[90],"last-stage":[92],"arbiters":[93],"been":[95],"investigated":[96],"in":[97],"detail.":[98],"Our":[99],"implemented":[100],"achieves":[102],"average":[103],"Uniformity,":[104],"Uniqueness,":[105],"Steadiness,":[106],"Min-Entropy,":[107],"Reliability":[109],"(evaluated":[110],"at":[111,137],"four":[112],"operating":[113],"temperatures)":[114],"metric":[115],"51.22%,":[118],"50.81%,":[119],"1.82%,":[120],"88.38%,":[121],"99.34%,":[123],"respectively.":[124],"A":[125],"software-based":[126],"fuzzy":[127],"error":[128],"correction":[129],"scheme":[130],"used":[132],"responses":[135],"generated":[136],"different":[138],"temperatures.":[139],"also":[143],"found":[144],"strongly":[147],"resistant":[148],"machine":[150],"learning":[151],"based":[152],"model-building":[153],"attacks,":[154],"Logistic":[156],"Regression":[157],"(LR)":[158],"Support":[160],"Vector":[161],"Machine":[162],"(SVM)":[163],"prediction":[164],"accuracies":[165],"51.22%":[167],"52.61%":[169],"respectively,":[170],"dataset":[173],"2,097,152":[175],"CRPs":[176],"using":[177,187],"additive":[178],"delay":[179],"models":[180],"analysis":[184],"performed":[186],"MLP":[188],"modelling-attacks":[189],"pypuf":[192],"framework.":[193]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}